FDG6321C MOSFET transistor datasheet. Parameters and characteristics.

Type Designator: FDG6321C

Type of FDG6321C transistor: MOSFET

Type of control channel: N -Channel

Maximum power dissipation (Pd), W:

Maximum drain-source voltage |Uds|, V: 25V

Maximum gate-source voltage |Ugs|, V:

Maximum drain current |Id|, A: 0.5

Maximum junction temperature (Tj), °C:

Rise Time of FDG6321C transistor (tr), nS:

Drain-source Capacitance (Cd), pF:

Maximum drain-source on-state resistance (Rds), Ohm: 0.45

Package: SC70

Equivalent transistors for FDG6321C

FDG6321C PDF documents for downloads:

1.1. fdg6321c.pdf Size:72K _fairchild_semi

November 1998 FDG6321C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode field N-Ch 0.50 A, 25 V, RDS(ON) = 0.45 ? @ VGS= 4.5V. effect transistors are produced using Fairchild's proprietary, RDS(ON) = 0.60 ? @ VGS= 2.7 V. high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. P-Ch -0.41 A, -25 V,RDS(ON) = 1.1 ? @ VGS= -4.5V. This device has been designed especially for low voltage RDS(ON) = 1.5 ? @ VGS= -2.7V. applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, Very small package outline SC70-6. this dual digital FET can replace several different digital Very low level gate drive requirements allowing direct transistors, with different bias resistor values. operation in 3 V circuits(VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model

4.1. fdg6320c.pdf Size:73K _fairchild_semi

November 1998 FDG6320C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 ? @ VGS= 4.5 V, field effect transistors are produced using Fairchild's RDS(ON) = 5.0 ? @ VGS= 2.7 V. proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize P-Ch -0.14 A, -25V, RDS(ON) = 10 ? @ VGS= -4.5V, on-state resistance. This device has been designed RDS(ON) = 13 ? @ VGS= -2.7V. especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since Very small package outline SC70-6. bias resistors are not required, this dual digital FET can Very low level gate drive requirements allowing direct replace several different digital transistors, with different bias operation in 3 V circuits (VGS(th) < 1.5 V). resistor values. Gate-Source Zener for ESD ruggedness (>6kV Human Body Mode

4.2. fdg6322c.pdf Size:669K _fairchild_semi

June 2008 FDG6322C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 ? @ VGS= 4.5 V, field effect transistors are produced using Fairchild's RDS(ON) = 5.0 ? @ VGS= 2.7 V. proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize P-Ch -0.41 A,-25V, RDS(ON) = 1.1 ? @ VGS= -4.5V, on-state resistance. This device has been designed RDS(ON) = 1.5 ? @ VGS= -2.7V. especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since Very small package outline SC70-6. bias resistors are not required, this dual digital FET can Very low level gate drive requirements allowing direct replace several different digital transistors, with different bias operation in 3 V circuits (VGS(th) < 1.5 V). resistor values. Gate-Source Zener for ESD ruggedness (>6kV Human Body Model).

See also transistors datasheet: FDG6306P , FDG6308P , FDG6316P , FDG6317NZ , FDG6318P , FDG6318PZ , FDG6320C , FDG6320C , 2SK955 , FDG6321C , FDG6322C , FDG6322C , FDG6332C , FDG6332C , FDG6332C_F085 , FDG6332C_F085 , FDG6335N .

Keywords