FDG6332C MOSFET transistor datasheet. Parameters and characteristics.

Type Designator: FDG6332C

Type of FDG6332C transistor: MOSFET

Type of control channel: N -Channel

Maximum power dissipation (Pd), W:

Maximum drain-source voltage |Uds|, V: 20V

Maximum gate-source voltage |Ugs|, V:

Maximum drain current |Id|, A: 0.7

Maximum junction temperature (Tj), °C:

Rise Time of FDG6332C transistor (tr), nS:

Drain-source Capacitance (Cd), pF:

Maximum drain-source on-state resistance (Rds), Ohm: 0.3

Package: SC70

Equivalent transistors for FDG6332C

FDG6332C PDF documents for downloads:

1.1. fdg6332c.pdf Size:93K _fairchild_semi

September 2003 FDG6332C ? 20V N & P-Channel PowerTrench? MOSFETs General Description Features The N & P-Channel MOSFETs are produced using • Q1 0.7 A, 20V. RDS(ON) = 300 m? @ VGS = 4.5 V Fairchild Semiconductor’s advanced PowerTrench RDS(ON) = 400 m? @ VGS = 2.5 V process that has been especially tailored to minimize on-state resistance and yet maintain superior • Q2 –0.6 A, –20V. RDS(ON) = 420 m? @ VGS = –4.5 V switching performance. RDS(ON) = 630 m? @ VGS = –2.5 V These devices have been designed to offer exceptional power dissipation in a very small footprint • Low gate charge for applications where the bigger more expensive TSSOP-8 and SSOP-6 packages are impractical. • High performance trench technology for extremely low RDS(ON) Applications • SC70-6 package: small footprint (51% smaller than • DC/DC converter SSOT-6); low profile (1mm thick) • Load switch • LCD display inverter S G 1 6 D 2 5 D G Pin 1 S 3 4 SC70-6 Complementary Absolute Maxim

4.1. fdg6335n.pdf Size:66K _fairchild_semi

October 2001 FDG6335N ? 20V N-Channel PowerTrench? MOSFET General Description Features This N-Channel MOSFET has been designed • 0.7 A, 20 V. RDS(ON) = 300 m? @ VGS = 4.5 V specifically to improve the overall efficiency of DC/DC RDS(ON) = 400 m? @ VGS = 2.5 V converters using either synchronous or conventional switching PWM controllers. It has been optimized use • Low gate charge (1.1 nC typical) in small switching regulators, providing an extremely low RDS(ON) and gate charge (QG) in a small package. • High performance trench technology for extremely low RDS(ON) Applications • Compact industry standard SC70-6 surface mount • DC/DC converter package • Power management • Loadswitch S D G S 1 or 4 6 or 3 D G 2 or 5 5 or 2 G D G S Pin 1 3 or 6 4 or 1 D S SC70-6 Dual N-Channel The pinouts are symmetrical; pin 1 and pin 4 are interchangeable. Absolute Maximum Ratings TA=25oC unless otherwise noted Symbol Parameter Ratings Units VDSS Drain-Source Volta

5.1. fdg6303n.pdf Size:414K _fairchild_semi

September 2001 FDG6303N Dual N-Channel, Digital FET General Description Features 25 V, 0.50 A continuous, 1.5 A peak. These dual N-Channel logic level enhancement mode RDS(ON) = 0.45 ? @ VGS= 4.5 V, field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This RDS(ON) =0.60 ? @ VGS= 2.7 V. very high density process is especially tailored to Very low level gate drive requirements allowing direct minimize on-state resistance. This device has been operation in 3 V circuits (VGS(th) < 1.5 V). designed especially for low voltage applications as a replacement for bipolar digital transistors and small Gate-Source Zener for ESD ruggedness signal MOSFETs. (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package. SOT-23 SuperSOTTM-6 SO-8 SC70-6 SuperSOTTM-8 SOT-223 S2 1 or 4 * 6 or 3 G2 D1 2 or 5 5 or 2 D2 G1 S1 4 or 1 * 3 or 6 SC70-6 * The pinouts are symmetrical; pin 1 and 4 are interc

5.2. fdg6320c.pdf Size:73K _fairchild_semi

November 1998 FDG6320C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 ? @ VGS= 4.5 V, field effect transistors are produced using Fairchild's RDS(ON) = 5.0 ? @ VGS= 2.7 V. proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize P-Ch -0.14 A, -25V, RDS(ON) = 10 ? @ VGS= -4.5V, on-state resistance. This device has been designed RDS(ON) = 13 ? @ VGS= -2.7V. especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since Very small package outline SC70-6. bias resistors are not required, this dual digital FET can Very low level gate drive requirements allowing direct replace several different digital transistors, with different bias operation in 3 V circuits (VGS(th) < 1.5 V). resistor values. Gate-Source Zener for ESD ruggedness (>6kV Human Body Mode

5.3. fdg6322c.pdf Size:669K _fairchild_semi

June 2008 FDG6322C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 ? @ VGS= 4.5 V, field effect transistors are produced using Fairchild's RDS(ON) = 5.0 ? @ VGS= 2.7 V. proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize P-Ch -0.41 A,-25V, RDS(ON) = 1.1 ? @ VGS= -4.5V, on-state resistance. This device has been designed RDS(ON) = 1.5 ? @ VGS= -2.7V. especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since Very small package outline SC70-6. bias resistors are not required, this dual digital FET can Very low level gate drive requirements allowing direct replace several different digital transistors, with different bias operation in 3 V circuits (VGS(th) < 1.5 V). resistor values. Gate-Source Zener for ESD ruggedness (>6kV Human Body Model).

5.4. fdg6306p.pdf Size:61K _fairchild_semi

February 2001 FDG6306P P-Channel 2.5V Specified PowerTrench MOSFET General Description Features This P 2.5V specified MOSFET is a rugged -Channel • –0.6 A, –20 V. R = 420 m? @ V = –4.5 V DS(ON) GS gate version of Fairchild Semiconductor’s advanced R = 630 m? @ V = –2.5 V DS(ON) GS PowerTrench process. It has been optimized for power management applications wi a wide range of gate th • Low gate charge drive voltage (2.5V – 12V). • High performance trench technology for extremely Applications low R DS(ON) • Battery management • Compact industry standard SC70-6 surface mount • Load switch package S G S D 1 or 4 6 or 3 D G G 2 or 5 5 or 2 D G 4 or 1 Pin 1 D 3 or 6 S S SC70-6 The pinouts are symmetrical; pin 1 and pin 4 are interchangeable. Absolute Maximum Ratings TA=25oC unless otherwise noted Symbol Parameter Ratings Units V Drain-Source Voltage –20 V DSS V Gate-Source Voltage ± 12 V GSS I Drain Current – Continuous

5.5. fdg6318p.pdf Size:123K _fairchild_semi

January 2003 FDG6318P Dual P-Channel, Digital FET General Description Features These dual P-Channel logic level enhancement mode • –0.5 A, –20 V. RDS(ON) = 780 m? @ VGS = –4.5 V MOSFET are produced using Fairchild Semiconductor’s RDS(ON) = 1200 m? @ VGS = –2.5 V advanced PowerTrench process that has been especially tailored to minimize on-state resistance. This device has been designed especially for low voltage • Very low level gate drive requirements allowing direct applications as a replacement for bipolar digital transistors and small signal MOSFETS. operation in 3V circuits (VGS(th) < 1.5V). Applications • Compact industry standard SC70-6 surface mount package • Battery management S G S D 1 or 4 6 or 3 D G G 2 or 5 5 or 2 D G 4 or 1 Pin 1 D 3 or 6 S S SC70-6 The pinouts are symmetrical; pin 1 and pin 4 are interchangeable. Absolute Maximum Ratings TA=25oC unless otherwise noted Symbol Parameter Ratings Units VDSS Drain-Sourc

5.6. fdg6302p.pdf Size:179K _fairchild_semi

July 1999 FDG6302P Dual P-Channel, Digital FET General Description Features -25 V, -0.14 A continuous, -0.4 A peak. These dual P-Channel logic level enhancement mode RDS(ON) = 10 ? @ VGS= -4.5 V, field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This RDS(ON) = 13 ? @ VGS= -2.7 V. very high density process is especially tailored to Very low level gate drive requirements allowing direct minimize on-state resistance. This device has been operation in 3 V circuits (VGS(th) < 1.5 V). designed especially for low voltage applications as a replacement for bipolar digital transistors and small Gate-Source Zener for ESD ruggedness signal MOSFETs. (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package. SOT-23 SuperSOTTM-6 SO-8 SC70-6 SuperSOTTM-8 SOT-223 S2 G2 1 or 4 * 6 or 3 D1 2 or 5 5 or 2 D2 . G1 S1 SC70-6 4 or 1 * 3 or 6 *The pinouts are symmetrical; pin 1 and 4 are inte

5.7. fdg6317nz.pdf Size:344K _fairchild_semi

May 2009 FDG6317NZ Dual 20v N-Channel PowerTrench MOSFET General Description Features This dual N-Channel MOSFET has been designed • 0.7 A, 20 V. RDS(ON) = 400 m? @ VGS = 4.5 V specifically to improve the overall efficiency of DC/DC RDS(ON) = 550 m? @ VGS = 2.5 V converters using either synchronous or conventional switching PWM controllers. It has been optimized use • Gate-Source Zener for ESD ruggedness in small switching regulators, providing an extremely (1.6kV Human Body Model). (Note 3) low RDS(ON) and gate charge (QG) in a small package. • Low gate charge Applications • High performance trench technology for extremely • DC/DC converter low RDS(ON) • Power management • Compact industry standard SC70-6 surface mount • Load switch package • RoHS Compliant S G D D G Pin 1 S SC70-6 The pinouts are symmetrical; pin 1 and pin 4 are interchangeable. Absolute Maximum Ratings TA=25oC unless otherwise noted Symbol Parameter Ratings Units VDSS Drain-Sourc

5.8. fdg6301n_f085.pdf Size:346K _fairchild_semi

March 2009 FDG6301N_F085 Dual N-Channel, Digital FET General Description Features 25 V, 0.22 A continuous, 0.65 A peak. These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's RDS(ON) = 4 ? @ VGS= 4.5 V, proprietary, high cell density, DMOS technology. This RDS(ON) = 5 ? @ VGS= 2.7 V. very high density process is especially tailored to Very low level gate drive requirements allowing direct minimize on-state resistance. This device has been operation in 3 V circuits (VGS(th) < 1.5 V). designed especially for low voltage applications as a replacement for bipolar digital transistors and small Gate-Source Zener for ESD ruggedness signal MOSFETs. (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package. Qualified to AEC Q101 RoHS Compliant SOT-23 SuperSOTTM-6 SO-8 SC70-6 SuperSOTTM-8 SOT-223 S2 1 or 4 * G2 6 or 3 D1 2 or 5 5 or 2 D2 G1 S1 4 or 1 * 3 or 6 SC70-6 *The pinouts a

5.9. fdg6304p.pdf Size:104K _fairchild_semi

July 1999 FDG6304P Dual P-Channel, Digital FET General Description Features -25 V, -0.41 A continuous, -1.5 A peak. These dual P-Channel logic level enhancement mode RDS(ON) = 1.1 ? @ VGS= -4.5 V, field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This RDS(ON) = 1.5 ? @ VGS= -2.7 V. very high density process is especially tailored to Very low level gate drive requirements allowing direct minimize on-state resistance. This device has been operation in 3 V circuits (VGS(th) < 1.5 V). designed especially for low voltage applications as a replacement for bipolar digital transistors and small Gate-Source Zener for ESD ruggedness signal MOSFETs. (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package. SO-8 SOT-23 SuperSOTTM-6 SC70-6 SuperSOTTM-8 SOT-223 S2 G2 1 or 4 * 6 or 3 D1 2 or 5 5 or 2 D2 G1 S1 SC70-6 4 or 1 * 3 or 6 *The pinouts are symmetrical; pin 1 and 4 are inter

5.10. fdg6321c.pdf Size:72K _fairchild_semi

November 1998 FDG6321C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode field N-Ch 0.50 A, 25 V, RDS(ON) = 0.45 ? @ VGS= 4.5V. effect transistors are produced using Fairchild's proprietary, RDS(ON) = 0.60 ? @ VGS= 2.7 V. high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. P-Ch -0.41 A, -25 V,RDS(ON) = 1.1 ? @ VGS= -4.5V. This device has been designed especially for low voltage RDS(ON) = 1.5 ? @ VGS= -2.7V. applications as a replacement for bipolar digital transistors and small signal MOSFETS. Since bias resistors are not required, Very small package outline SC70-6. this dual digital FET can replace several different digital Very low level gate drive requirements allowing direct transistors, with different bias resistor values. operation in 3 V circuits(VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model

5.11. fdg6308p.pdf Size:85K _fairchild_semi

October 2000 PRELIMINARY FDG6308P ? ? ? P-Channel 1.8V Specified PowerTrench? MOSFET General Description Features This P-Channel 1.8V specified MOSFET uses • –0.6 A, –20 V. RDS(ON) = 0.40 ? @ VGS = –4.5 V Fairchild’s advanced low voltage PowerTrench process. RDS(ON) = 0.55 ? @ VGS = –2.5 V It has been optimized for battery power management RDS(ON) = 0.80 ? @ VGS = –1.8 V applications. • Low gate charge Applications • High performance trench technology for extremely • Battery management low RDS(ON) • Load switch • Compact industry standard SC70-6 surface mount package S G S D 1 or 4 6 or 3 D G G 2 or 5 5 or 2 D G 4 or 1 Pin 1 D 3 or 6 S S SC70-6 The pinouts are symmetrical; pin 1 and pin 4 are interchangeable. Absolute Maximum Ratings TA=25oC unless otherwise noted Symbol Parameter Ratings Units VDSS Drain-Source Voltage –20 V VGSS Gate-Source Voltage ± 8 V ID Drain Current – Continuous (Note 1) –0.6 A – Pulsed –1.8 PD Power Dissipation for Sing

5.12. fdg6301n.pdf Size:103K _fairchild_semi

July 1999 FDG6301N Dual N-Channel, Digital FET General Description Features 25 V, 0.22 A continuous, 0.65 A peak. These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's RDS(ON) = 4 ? @ VGS= 4.5 V, proprietary, high cell density, DMOS technology. This RDS(ON) = 5 ? @ VGS= 2.7 V. very high density process is especially tailored to Very low level gate drive requirements allowing direct minimize on-state resistance. This device has been operation in 3 V circuits (VGS(th) < 1.5 V). designed especially for low voltage applications as a replacement for bipolar digital transistors and small Gate-Source Zener for ESD ruggedness signal MOSFETs. (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package. SOT-23 SuperSOTTM-6 SO-8 SC70-6 SuperSOTTM-8 SOT-223 S2 1 or 4 * G2 6 or 3 D1 2 or 5 5 or 2 D2 G1 S1 4 or 1 * 3 or 6 SC70-6 *The pinouts are symmetrical; pin 1 and 4 are interchangeabl

5.13. fdg6316p.pdf Size:149K _fairchild_semi

December 2001 FDG6316P ? ? ? P-Channel 1.8V Specified PowerTrench? MOSFET General Description Features This P-Channel 1.8V specified MOSFET uses • –0.7 A, –12 V. RDS(ON) = 270 m? @ VGS = –4.5 V Fairchild’s advanced low voltage PowerTrench process. RDS(ON) = 360 m? @ VGS = –2.5 V It has been optimized for battery power management RDS(ON) = 650 m? @ VGS = –1.8 V applications. • Low gate charge Applications • High performance trench technology for extremely • Battery management low RDS(ON) • Load switch • Compact industry standard SC70-6 surface mount package S G S D 1 or 4 6 or 3 D G G 2 or 5 5 or 2 D G 4 or 1 Pin 1 D 3 or 6 S S SC70-6 The pinouts are symmetrical; pin 1 and pin 4 are interchangeable. Absolute Maximum Ratings TA=25oC unless otherwise noted Symbol Parameter Ratings Units VDSS Drain-Source Voltage –12 V VGSS Gate-Source Voltage ± 8 V ID Drain Current – Continuous (Note 1) –0.7 A – Pulsed –1.8 PD Power Dissipat

See also transistors datasheet: FDG6318PZ , FDG6320C , FDG6320C , FDG6321C , FDG6321C , FDG6322C , FDG6322C , FDG6332C , IRF511 , FDG6332C_F085 , FDG6332C_F085 , FDG6335N , FDG8842CZ , FDG8842CZ , FDG8842CZ , FDG8850NZ , FDG8850NZ .

Keywords