View 74lvc109 3 datasheet:

INTEGRATED CIRCUITS 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification 1998 Apr 28 Supersedes data of 1997 Mar 18 IC24 Data Handbook Philips Semiconductors Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LVC109 FEATURES DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and • Wide supply voltage range of 1.2 to 3.6 V function compatible with 74HC/HCT109. • In accordance with JEDEC standard no. 8-1A. The 74LVC109 is a dual positive-edge triggered JK-type flip-flop • Inputs accept voltages up to 5.5 V featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. • CMOS low power consumption T