View 74lvc573a datasheet:

74LVC573A OCTAL D-TYPE LATCH HIGH PERFORMANCE 5V TOLERANT INPUTS HIGH SPEED: tPD = 6.8ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V SOP TSSOP PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ? tPHL ORDER CODES OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 3.6V (1.2V Data PACKAGE TUBE T & R Retention) SOP 74LVC573AM 74LVC573AMTR PIN AND FUNCTION COMPATIBLE WITH TSSOP 74LVC573ATTR 74 SERIES 573 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) outputs will follow the data input precisely or ESD PERFORMANCE: inversely. When the LE is taken low, the Q outputs HBM > 2000V (MIL STD 883 method 3015); will be latched precisely or inversely at the logic MM