View imsa110 datasheet:

IMSA110 IMAGE AND SIGNAL PROCESSING SUB–SYSTEM . 1-D/2-D SOFTWARE CONFIGURABLE CON- VOLVER/FILTER . ON-CHIP PROGRAMMABLE LINE DELAYS (0 — 1120 STAGES) . 8-BIT DATA AND 8.5-BIT COEFFICIENT SLICE . 21 MULTIPLY-AND-ACCUMULATE STAGES . 1-D (21) OR 2-D (3 x 7) CONVOLUTION WIN- DOW . ON-CHIP POST PROCESSOR FOR DATA TRANSFORMATION . FULLY CASCADABLE IN WINDOW SIZE AND ACCURACY . 20 MHZ DATA THROUGHPUT (420 MOPS) . SIGNED/UNSIGNED DATA AND COEFFI- CIENTS . MICROPROCESSOR INTERFACE . HIGH SPEED CMOS IMPLEMENTATION . TTL COMPATIBLE . SINGLE +5V ± 10% SUPPLY . POWER DISSIPATION < 2.0 WATTS PGA100 . 100 PIN CERAMIC PGA (Ceramic Grid Array Package) APPLICATIONS . 1-D and 2-D digital convolution and correlation . Real time image processing and enhancement .