View lh521028 datasheet:

LH521028 CMOS 64K ? 18 Static RAM operations on the high and the low bytes. The Address FEATURES Latches are transparent when ALE is HIGH (for applica- • Fast Access Times: 17/20/25/35 ns • tions not requiring a latch), and are latched when ALE is LOW. The Address Latches and the wide word help to • Wide Word (18-Bits) for: • eliminate the need for external Address busbuffers and/or – Improved Performance latches. – Reduced Component Count Write cycles occur when Chip Enable (E), S and/or H – Nine-bit Byte for Parity S , and Write Enable (W) are LOW. The Byte-select L signals can be used for Byte-write operations by disabling • Transparent Address Latch • the other byte during the Write operation. Data is trans- ferred from the DQ pins to the memory location specifi