View lh521028a datasheet:

LH521028A CMOS 64K ? 18 Static RAM and S , are also used to enable or disable Read and Write L FEATURES operations on the high and the low bytes. The Address • Fast Access Times: 15/17/20/25/35 ns • Latches are transparent when ALE is HIGH (for applica- tions not requiring a latch), and are latched when ALE is • Wide Word (18-Bits) for: • LOW. The Address Latches and the wide word help to – Improved Performance eliminate the need for external Address bus buffers and/or – Reduced Component Count latches. – Nine-bit Byte for Parity Write cycles occur when Chip Enable (E), S and/or H S , and Write Enable (W) are LOW. The Byte-select L • Transparent Address Latch • signals can be used for Byte-write operations by disabling the other byte during the Write operation. Data