View 74ahc74 datasheet:

SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS255G – DECEMBER 1995 – REVISED JANUARY 20000 SN54AHC74 . . . J OR W PACKAGE D EPIC? (Enhanced-Performance Implanted SN74AHC74 . . . D, DB, DGV, N, OR PW PACKAGE CMOS) Process (TOP VIEW) D Operating Range 2-V to 5.5-V VCC D Latch-Up Performance Exceeds 250 mA Per 1CLR VCC 1 14 JESD 17 1D 2CLR 2 13 D ESD Protection Exceeds 2000 V Per 1CLK 2D 3 12 MIL-STD-883, Method 3015; Exceeds 200 V 1PRE 4 11 2CLK Using Machine Model (C = 200 pF, R = 0) 1Q 5 10 2PRE 1Q 6 9 2Q D Package Options Include Plastic 7 8 GND 2Q Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), and Ceramic SN54AHC74 . . . FK PACKAGE Flat (W) Packages,