View phb50n06lt datasheet:

Philips Semiconductors Product specification TrenchMOS? transistor PHB50N06LT Logic level FET GENERAL DESCRIPTION QUICK REFERENCE DATA N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT level field-effect power transistor in a plastic envelope suitable for surface VDS Drain-source voltage 55 V mounting. Using ’trench’ technology ID Drain current (DC) 50 A the device features very low on-state Ptot Total power dissipation 125 W resistance and has integral zener Tj Junction temperature 175 ?C diodes giving ESD protection up to RDS(ON) Drain-source on-state 24 m? 2kV. It is intended for use in DC-DC resistance VGS = 5 V converters and general purpose switching applications. PINNING - SOT404 PIN CONFIGURATION SYMBOL PIN DESCRIPTION d mb 1 gate 2 drain g 3 source