View sda92542 datasheet:

2.6 MBit Dynamic Sequential Access Memory SDA 9254-2 for Television Applications (TV-SAM) with On-chip Noise Reduction Filter Preliminary Data CMOS IC Features Stores a complete video field (4:1:1) On chip adaptive recursive noise reduction filter (4:1:1) 4 noise reduction classes selectable Special noise reduction mode for 4:2:2 applications 212 ? 64 ? 16 ? 12-bit organization Triple port architecture One 16 ? 12-bit input shift register Two 16 ? 12-bit output shift registers P-MQFP-64-1 Shift registers independently and simultaneously accessible (one output shift register is used internally for noise reduction filtering) Continuous data flow even at maximum speed 40-MHz shift rate - 0.96-Gbit/s total data rate All inputs and outputs TTL-compatible Tristat