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GS809C and GS810C Microprocessor Reset Monitors Pin Configuration Description SOT-23 (Top View) • The GS809C and 810C are system supervisor circuits designed to monitor V in digital systems CC GND 1 and provide a reset signal to the host processor when necessary. No external components are 3 V cc required. • When the processor power supply voltage drops Reset 2 Output below the reset threshold, the reset output is driven active, in less than 40µs (T ). Reset is main- D1 tained active for a time period (T ), after the V D2 cc rises above the threshold voltage. Fig. 1 – Typical Application Diagram • To prevent jitter, the reset threshold voltage has a built-in hysteresis of 0.4% of V . TH VCC • The GS809C has an active-low reset output, while the GS8