HUF75229P3 Todos los transistores

HUF75229P3 Data Sheet December 2001 44A, 50V, 0.022 Ohm, N-Channel UltraFET Features Power MOSFET 44A, 50V This N-Channel power MOSFET is Low On-Resistance, rDS(ON) = 0.022 manufactured using the innovative Temperature Compensating PSPICE Model UltraFET process. This advanced process technology achieves the Thermal Impedance SPICE Model lowest possible on-

HUF75852G3 Data Sheet December 2001 75A, 150V, 0.016 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC TO-247 Features SOURCE Ultra Low On-Resistance DRAIN GATE - rDS(ON) = 0.016 , VGS = 10V Simulation Models - Temperature Compensated PSPICE and SABER Electrical Models - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com DRAIN (TAB) Pe

HUF75321P3, HUF75321S3S Data Sheet December 2001 35A, 55V, 0.034 Ohm, N-Channel UltraFET Features Power MOSFETs 35A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Models advanced process technology - Thermal Impedance SPICE and SABER Models achieves the

HUF75623P3, HUF75623S3ST Data Sheet December 2001 22A, 100V, 0.064 Ohm, N-Channel, UltraFET Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN Ultra Low On-Resistance (FLANGE) GATE - rDS(ON) = 0.064 , VGS = 10V Simulation Models GATE - Temperature Compensated PSPICE and SABER SOURCE Electrical Models DRAIN - Spice and SABER T

HUF75329D3S Data Sheet October 2013 N-Channel UltraFET Power MOSFET Features 55 V, 20 A, 26 m 20A, 55V These N-Channel power MOSFETs are manufactured using Simulation Models the innovative UltraFET process. This advanced process - Temperature Compensated PSPICE and SABER technology achieves the lowest possible on-resistance per Models silicon area, resulting in ou

HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Data Sheet December 2001 56A, 100V, 0.025 Ohm, N-Channel Features UltraFET Power MOSFETs 56A, 100V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Electrical Models advanced process technology - Spice and Saber T

HUF75631SK8 Data Sheet December 2001 5.5A, 100V, 0.039 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC MS-012AA Features BRANDING DASH Ultra Low On-Resistance - rDS(ON) = 0.039 , VGS = 10V 5 Simulation Models 1 - Temperature Compensated PSPICE and SABER 2 Electrical Models 3 4 - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com Symbol

HUF75842P3, HUF75842S3S Data Sheet December 2001 43A, 150V, 0.042 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN Ultra Low On-Resistance DRAIN (FLANGE) GATE - rDS(ON) = 0.042 , VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER Electrical Models DRAIN - Spice and SABER Therm

HUFA75639S3ST_F085A Data Sheet March 2012 56A, 100V, 0.025 Ohm, N-Channel Features UltraFET Power MOSFETs 56A, 100V These N-Channel power MOSFETs Peak Current vs Pulse Width Curve are manufactured using the UIS Rating Curve innovative UltraFET process. This advanced process technology Related Literature achieves the lowest possible on-resistance per silicon ar

October 2007 HUF75344A3 tm N-Channel UltraFET Power MOSFET 55V, 75A, 8m Features Description RDS(on) = 6.5m ( Typ.)@ VGS = 10V, ID = 75A This N-channel power MOSFET is produced using Fairchild Semiconductor s innovative UItraFET process. This advanced RoHS compliant process technology achieves the lowest possible on-resistance per silicon area, resulting in outstan

HUF75645P3, HUF75645S3S Data Sheet December 2001 75A, 100V, 0.014 Ohm, N-Channel, UltraFET Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN Ultra Low On-Resistance (FLANGE) GATE - rDS(ON) = 0.014 , VGS = 10V GATE Simulation Models - Temperature Compensated PSPICE and SABER SOURCE Electrical Models DRAIN - Spice and Saber Th

HUF75343G3, HUF75343P3, HUF75343S3S Data Sheet December 2001 75A, 55V, 0.009 Ohm, N-Channel UltraFET Features Power MOSFETs 75A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensating PSPICE and SABER innovative UltraFET process. This Models advanced process technology - Thermal Impedance PSPICE and SABER Mode

HUF75343G3, HUF75343P3, HUF75343S3, HUF75343S3S Data Sheet March 2003 75A, 55V, 0.009 Ohm, N-Channel UltraFET Features Power MOSFETs 75A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensating PSPICE and SABER innovative UltraFET process. This Models advanced process technology - Thermal Impedance PSPICE and

HUFA75852G3_F085 Data Sheet December 2011 75A, 150V, 0.016 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC TO-247 Features SOURCE Ultra Low On-Resistance DRAIN GATE - rDS(ON) = 0.016 , VGS = 10V Peak Current vs Pulse Width Curve UIS Rating Curve Qualified to AEC Q101 RoHS Compliant DRAIN (TAB) Ordering Information Symbol PART NUMBER PACKAGE BRA

HUF75309T3ST Data Sheet December 2001 3A, 55V, 0.070 Ohm, N-Channel UltraFET Features Power MOSFET 3A, 55V This N-Channel power MOSFET is Ultra Low On-Resistance, rDS(ON) = 0.070 manufactured using the innovative Diode Exhibits Both High Speed and Soft Recovery UltraFET process. This advanced process technology achieves the Temperature Compensating PSPICE M

HUF75652G3 Data Sheet December 2001 75A, 100V, 0.008 Ohm, N-Channel UltraFET Power MOSFET Packaging JEDEC TO-247 Features SOURCE DRAIN Ultra Low On-Resistance GATE - rDS(ON) = 0.008 , VGS = 10V Simulation Models - Temperature Compensated PSPICE and SABER Electrical Models - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com DRAIN HUF75652G3 (T

HUF75631P3, HUF75631S3ST Data Sheet December 2001 33A, 100V, 0.040 Ohm, N-Channel, UltraFET Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN (FLANGE) Ultra Low On-Resistance GATE - rDS(ON) = 0.040 , VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER Electrical Models DRAIN (FLANGE) - Spice an

HUF75531SK8 Data Sheet December 2001 6A, 80V, 0.030 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC MS-012AA Features BRANDING DASH Ultra Low On-Resistance - rDS(ON) = 0.030 , VGS = 10V Simulation Models 5 - Temperature Compensated PSPICE and SABER 1 Electrical Models 2 3 - Spice and SABER Thermal Impedance Models 4 - www.fairchildsemi.com Peak Curren

HUF75631SK8 Data Sheet December 2001 5.5A, 100V, 0.039 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC MS-012AA Features BRANDING DASH Ultra Low On-Resistance - rDS(ON) = 0.039 , VGS = 10V 5 Simulation Models 1 - Temperature Compensated PSPICE and SABER 2 Electrical Models 3 4 - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com Symbol

HUF75329D3, HUF75329D3S Data Sheet December 2001 20A, 55V, 0.026 Ohm, N-Channel UltraFET Features Power MOSFETs 20A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Models advanced process technology - SPICE and SABER Thermal Impedance Models achieves the

HUF75939P3, HUF75939S3ST Data Sheet December 2001 22A, 200V, 0.125 Ohm, N-Channel, UltraFET Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB Ultra Low On-Resistance SOURCE DRAIN rDS(ON) = 0.125 , VGS = 10V DRAIN (FLANGE) GATE Simulation Models GATE - Temperature Compensated PSPICE and SABER Electrical Models SOURCE - Spice and SABER Thermal

HUF75831SK8 Data Sheet December 2001 3A, 150V, 0.095 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC MS-012AA Features BRANDING DASH Ultra Low On-Resistance - rDS(ON) = 0.095 , VGS = 10V Simulation Models 5 - Temperature Compensated PSPICE and SABER 1 Electrical Models 2 - Spice and SABER Thermal Impedance Models 3 4 - www.fairchildsemi.com Peak

HUF75842P3, HUF75842S3S Data Sheet December 2001 43A, 150V, 0.042 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN Ultra Low On-Resistance DRAIN (FLANGE) GATE - rDS(ON) = 0.042 , VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER Electrical Models DRAIN - Spice and SABER Therm

HUF75545P3, HUF75545S3, HUF75545S3S Data Sheet September 2002 75A, 80V, 0.010 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC TO-220AB JEDEC TO-263AB DRAIN Features SOURCE (FLANGE) DRAIN GATE Ultra Low On-Resistance - rDS(ON) = 0.010 , VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER DRAIN Electrical Models (FLANG

HUF75333G3, HUF75333P3, HUF75333S3S, HUF75333S3 Data Sheet December 2001 66A, 55V, 0.016 Ohm. N-Channel UltraFET Features Power MOSFETs 66A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Models advanced process technology - SPICE and SABER Thermal Impeda

HUF75637P3, HUF75637S3S Data Sheet December 2001 44A, 100V, 0.030 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN (FLANGE) Ultra Low On-Resistance GATE - rDS(ON) = 0.030 , VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER Electrical Models DRAIN (FLANGE) - Spice and S

HUF75545P3, HUF75545S3, HUF75545S3S Data Sheet September 2002 75A, 80V, 0.010 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC TO-220AB JEDEC TO-263AB DRAIN Features SOURCE (FLANGE) DRAIN GATE Ultra Low On-Resistance - rDS(ON) = 0.010 , VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER DRAIN Electrical Models (FLANG

HUF75637P3, HUF75637S3S Data Sheet December 2001 44A, 100V, 0.030 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN (FLANGE) Ultra Low On-Resistance GATE - rDS(ON) = 0.030 , VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER Electrical Models DRAIN (FLANGE) - Spice and S

HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Data Sheet December 2001 56A, 100V, 0.025 Ohm, N-Channel Features UltraFET Power MOSFETs 56A, 100V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Electrical Models advanced process technology - Spice and Saber T

HUF75337G3, HUF75337P3, HUF75337S3S Data Sheet December 2001 75A, 55V, 0.014 Ohm, N-Channel UltraFET Features Power MOSFETs 75A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Models advanced process technology - SPICE and SABER Thermal Impedance Models

HUF75332G3, HUF75332P3, HUF75332S3S Data Sheet January 2005 60A, 55V, 0.019 Ohm, N-Channel UltraFET Features Power MOSFETs 60A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Models advanced process technology - SPICE and SABER Thermal Impedance Models a

HUF75307T3ST Data Sheet December 2001 2.6A, 55V, 0.090 Ohm, N-Channel UltraFET Features Power MOSFET 2.6A, 55V This N-Channel power MOSFET is Ultra Low On-Resistance, rDS(ON) = 0.090 manufactured using the innovative Diode Exhibits Both High Speed and Soft Recovery UltraFET process. This advanced process technology achieves the Temperature Compensating PSPICE

HUF75542P3, HUF75542S3S Data Sheet December 2001 75A, 80V, 0.014 Ohm, N-Channel, UltraFET Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN Ultra Low On-Resistance GATE - rDS(ON) = 0.014 , VGS = 10V Simulation Models GATE - Temperature Compensated PSPICE and SABER SOURCE Electrical Models DRAIN - Spice and SABER Thermal Impedance Model

HUF75329G3, HUF75329P3, HUF75329S3S Data Sheet December 2001 49A, 55V, 0.024 Ohm, N-Channel UltraFET Features Power MOSFETs 49A, 55V These N-Channel power MOSFETs Ultra Low On-Resistance, rDS(ON) = 0.024 are manufactured using the Temperature Compensating PSPICE and SABER innovative UltraFET process. This Models advanced process technology - Available on t

HUF75645P3, HUF75645S3S Data Sheet December 2001 75A, 100V, 0.014 Ohm, N-Channel, UltraFET Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN Ultra Low On-Resistance (FLANGE) GATE - rDS(ON) = 0.014 , VGS = 10V GATE Simulation Models - Temperature Compensated PSPICE and SABER SOURCE Electrical Models DRAIN - Spice and Saber Th

HUF75345G3, HUF75345P3, HUF75345S3S Data Sheet December 2009 75A, 55V, 0.007 Ohm, N-Channel UltraFET Features Power MOSFETs 75A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Models advanced process technology - Thermal Impedance SPICE and SABER Models

HUFA75829D3, HUFA75829D3S Data Sheet December 2001 18A, 150V, 0.110 Ohm, N-Channel, UltraFET Power MOSFETs Packaging JEDEC TO-251AA JEDEC TO-252AA Features DRAIN Ultra Low On-Resistance SOURCE (FLANGE) DRAIN - rDS(ON) = 0.110 , VGS = 10V GATE GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER Electrical Models DRAIN (FLANGE) - Spice

HUF75339G3, HUF75339P3, HUF75339S3S Data Sheet December 2001 75A, 55V, 0.012 Ohm, N-Channel UltraFET Features Power MOSFETs 75A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Models advanced process technology - SPICE and SABER Thermal Impedance Models

HUF75617D3, HUF75617D3S Data Sheet December 2001 16A, 100V, 0.090 Ohm, N-Channel, UltraFET Power MOSFETs Packaging JEDEC TO-251AA JEDEC TO-252AA Features Ultra Low On-Resistance SOURCE DRAIN DRAIN - rDS(ON) = 0.090 , VGS = 10V (FLANGE) GATE Simulation Models GATE - Temperature Compensated PSPICE and SABER SOURCE Electrical Models DRAIN (FLANGE) - Spice

HUF75631P3, HUF75631S3ST Data Sheet December 2001 33A, 100V, 0.040 Ohm, N-Channel, UltraFET Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN (FLANGE) Ultra Low On-Resistance GATE - rDS(ON) = 0.040 , VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER Electrical Models DRAIN (FLANGE) - Spice an

HUF75925D3ST Data Sheet August 2004 11A, 200V, 0.275 Ohm, N-Channel, UltraFET Power MOSFET Packaging Features Ultra Low On-Resistance - rDS(ON) = 0.275 , VGS = 10V DRAIN (FLANGE) Simulation Models - Temperature Compensated PSPICE and SABER GATE Electrical Models SOURCE - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com HUF75925D3ST Peak

MOSFET Power, N-Channel, UltraFET 55 V, 75 A, 7 mW HUF75345G3, HUF75345P3, HUF75345S3S www.onsemi.com Description These N-Channel power MOSFETs are manufactured using VDSS RDS(ON) MAX ID MAX the innovative UltraFET process. This advanced process technology 55 V 7 mW 75 A achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This devic

Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclatur

Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclatur

HUF75545P3, HUF75545S3S Data Sheet October 2013 N-Channel UltraFET Power MOSFET 80 V, 75 A, 10 m Features Packaging Ultra Low On-Resistance - rDS(ON) = 0.010 , VGS = 10V JEDEC TO-220AB JEDEC TO-263AB DRAIN Simulation Models SOURCE (FLANGE) DRAIN - Temperature Compensated PSPICE and SABER GATE Electrical Models GATE - Spice and SABER Thermal Impedance Models

HUF75329D3S Data Sheet October 2013 N-Channel UltraFET Power MOSFET Features 55 V, 20 A, 26 m 20A, 55V These N-Channel power MOSFETs are manufactured Simulation Models using the innovative UltraFET process. This advanced - Temperature Compensated PSPICE and SABER process technology achieves the lowest possible on- Models resistance per silicon area, resulting in o

MOSFET Power, N-Channel, Ultrafet 100 V, 75 A, 8 mW HUF75652G3 Features www.onsemi.com Ultra Low On-Resistance rDS(ON) = 0.008 W, VGS = 10 V Simulation Models D Temperature Compensated PSPICE and SABER Electrical Models Spice and SABER Thermal Impedance Models G www.onsemi.com Peak Current vs Pulse Width Curve S UIS Rating Curve Th

Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclatur

Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclatur

MOSFET Power, N-Channel, Ultrafet 100 V, 56 A, 25 mW HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 www.onsemi.com These N-Channel power MOSFETs are manufactured using the innovative Ultrafet process. This advanced process technology achieves the lowest possible on- resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high ener

HUF75344G3, HUF75344P3 Data Sheet October 2013 N-Channel UltraFET Power MOSFET Features 55 V, 75 A, 8 m 75A, 55V These N-Channel power MOSFETs are manufactured Simulation Models using the innovative UltraFET process. This advanced - Temperature Compensated PSPICE and SABER process technology achieves the lowest possible on- Models resistance per silicon area, result

HUF75645P3, HUF75645S3S Data Sheet October 2013 N-Channel UltraFET Power MOSFET 100 V, 75 A, 14 m Features Packaging Ultra Low On-Resistance - rDS(ON) = 0.014 , VGS = 10V JEDEC TO-220AB JEDEC TO-263AB Simulation Models SOURCE DRAIN - Temperature Compensated PSPICE and SABER DRAIN (FLANGE) GATE Electrical Models - Spice and Saber Thermal Impedance Models GATE

HUF75337G3, HUF75337P3, S E M I C O N D U C T O R HUF75337S3, HUF75337S3S 62A, 55V, 0.014 Ohm, N-Channel UltraFET Power MOSFETs January 1998 Features Description 62A, 55V These N-Channel power MOS- FETs are manufactured using Ultra Low On-Resistance, rDS(ON) = 0.014 the innovative UltraFET pro- cess. This advanced process technology achieves the low- Diode Exhibits

HUF75344G3, HUF75344P3, HUF75344S3S Data Sheet January 2000 File Number 4402.7 75A, 55V, 0.008 Ohm, N-Channel UltraFET Features Power MOSFETs 75A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. Models This advanced process technology - Thermal Impedance PSPICE and S

HUF75623P3 Data Sheet November 1999 File Number 4804 22A, 100V, 0.064 Ohm, N-Channel, UltraFET Power MOSFET Packaging Features JEDEC TO-220AB Ultra Low On-Resistance - rDS(ON) = 0.064 , VGS = 10V SOURCE DRAIN Simulation Models GATE - Temperature Compensated PSPICE and SABER Electrical Models - Spice and SABER Thermal Impedance Models - www.intersil.com DRAIN (

HUF75332G3, HUF75332P3, HUF75332S3S Data Sheet June 1999 File Number 4489.3 60A, 55V, 0.019 Ohm, N-Channel UltraFET Features Power MOSFETs 60A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. Models This advanced process technology - SPICE and SABER Thermal Impedance

HUF75321D3S www.VBsemi.tw N-Channel 6 0-V (D-S) MOSFET FEATURES PRODUCT SUMMARY TrenchFET Power MOSFET VDS (V) rDS(on) ( ) ID (A)a Available 175 C Junction Temperature 0.025 at VGS = 10 V 35 RoHS* 60 0.030 at VGS = 4.5 V 30 COMPLIANT TO-252 D G Drain Connected to Tab G D S S Top View N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS TC = 25 C, unless otherwise n

INCHANGE Semiconductor isc N-Channel MOSFET Transistor HUF75345S3ST DESCRIPTION Drain Current I = 75A@ T =25 D C Drain Source Voltage V = 55V(Min) DSS Fast Switching Speed Minimum Lot-to-Lot variations for robust device performance and reliable operation APPLICATIONS . Designed for high current, high speed switching, switch mode power supplies. ABSOLUTE MAXIMUM