HUF76639S3S Todos los transistores

HUF76639P3, HUF76639S3S Data Sheet December 2001 50A, 100V, 0.027 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB Ultra Low On-Resistance SOURCE DRAIN - rDS(ON) = 0.026 , VGS = 10V DRAIN (FLANGE) GATE - rDS(ON) = 0.027 , VGS = 5V Simulation Models GATE - Temperature Compensated PSPICE and SABER SOURCE Ele

Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclatur

HUF76639S3ST_F085 July 2012 50A, 100V, 0.026 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging Features JEDEC TO-263AB Ultra Low On-Resistance DRAIN - rDS(ON) = 0.026 , VGS = 10V (FLANGE) Simulation Models - Temperature Compensated PSPICE and SABER GATE Electrical Models SOURCE - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com

HUF76639P3, HUF76639S3S Data Sheet December 2001 50A, 100V, 0.027 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB Ultra Low On-Resistance SOURCE DRAIN - rDS(ON) = 0.026 , VGS = 10V DRAIN (FLANGE) GATE - rDS(ON) = 0.027 , VGS = 5V Simulation Models GATE - Temperature Compensated PSPICE and SABER SOURCE Ele

HUF76633P3_F085 Data Sheet April 2012 38A, 100V, 0.036 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging Features JEDEC TO-220AB Ultra Low On-Resistance - rDS(ON) = 0.035 , VGS = 10V SOURCE DRAIN - rDS(ON) = 0.036 , VGS = 5V GATE Simulation Models - Temperature Compensated PSPICE and SABER Electrical Models - Spice and SABER Thermal Impedance Model

HUF76633P3, HUF76633S3S Data Sheet December 2001 38A, 100V, 0.036 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB Ultra Low On-Resistance DRAIN SOURCE (FLANGE) - rDS(ON) = 0.035 , VGS = 10V DRAIN GATE - rDS(ON) = 0.036 , VGS = 5V Simulation Models GATE - Temperature Compensated PSPICE and SABER SOURCE El

HUF76633P3, HUF76633S3S Data Sheet December 2001 38A, 100V, 0.036 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB Ultra Low On-Resistance DRAIN SOURCE (FLANGE) - rDS(ON) = 0.035 , VGS = 10V DRAIN GATE - rDS(ON) = 0.036 , VGS = 5V Simulation Models GATE - Temperature Compensated PSPICE and SABER SOURCE El

HUF76633P3 www.VBsemi.tw N-Channel 100-V (D-S) MOSFET FEATURES PRODUCT SUMMARY TrenchFET Power MOSFETS V(BR)DSS (V) rDS(on) ( )ID (A) Available 175 C Junction Temperature 0.032 at VGS = 10 V 45 RoHS* 100 Low Thermal Resistance Package 0.035 at VGS = 4.5 V 40 COMPLIANT D TO-220AB G S G D S Top View N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS TC = 25 C,