HUF75617D3 Todos los transistores

 

HUF75617D3 MOSFET. Datasheet. Equivalente. Reemplazo. Hoja de especificaciones. Principales características

Número de Parte: HUF75617D3

Código: 75617D

Tipo de FET: MOSFET

Polaridad de transistor: N

ESPECIFICACIONES MÁXIMAS

Disipación total del dispositivo (Pd): 64 W

Tensión drenaje-fuente (Vds): 100 V

Tensión compuerta-fuente (Vgs): 20 V

Corriente continua de drenaje (Id): 16 A

Temperatura operativa máxima (Tj): 175 °C

CARACTERÍSTICAS ELÉCTRICAS

Tensión umbral compuerta-fuente Vgs(th): 4 V

Carga de compuerta (Qg): 31 nC

Tiempo de elevación (tr): 35 nS

Conductancia de drenaje-sustrato (Cd): 125 pF

Resistencia drenaje-fuente RDS(on): 0.09 Ohm

Empaquetado / Estuche: TO-251AA

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HUF75617D3 Datasheet (PDF)

1.1. huf75617d3st huf75617d3 huf75617d3s.pdf Size:196K _update_mosfet

HUF75617D3
HUF75617D3

 HUF75617D3, HUF75617D3S Data Sheet December 2001 16A, 100V, 0.090 Ohm, N-Channel, UltraFET® Power MOSFETs Packaging JEDEC TO-251AA JEDEC TO-252AA Features • Ultra Low On-Resistance SOURCE DRAIN DRAIN - rDS(ON) = 0.090Ω, VGS = 10V (FLANGE) GATE • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™ SOURCE Electrical Models DRAIN (FLANGE) - Spice

4.1. huf75631sk8t.pdf Size:249K _update_mosfet

HUF75617D3
HUF75617D3

 HUF75631SK8 Data Sheet December 2001 5.5A, 100V, 0.039 Ohm, N-Channel, UltraFET® Power MOSFET Packaging JEDEC MS-012AA Features BRANDING DASH • Ultra Low On-Resistance - rDS(ON) = 0.039Ω, VGS = 10V 5 • Simulation Models 1 - Temperature Compensated PSPICE® and SABER™ 2 Electrical Models 3 4 - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com Symbol

4.2. huf75623s3st.pdf Size:198K _update_mosfet

HUF75617D3
HUF75617D3

HUF75623P3, HUF75623S3ST Data Sheet December 2001 22A, 100V, 0.064 Ohm, N-Channel, UltraFET® Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN • Ultra Low On-Resistance (FLANGE) GATE - rDS(ON) = 0.064Ω, VGS = 10V • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™ SOURCE Electrical Models DRAIN - Spice and SABER T

 4.3. huf75631s3st.pdf Size:200K _update_mosfet

HUF75617D3
HUF75617D3

HUF75631P3, HUF75631S3ST Data Sheet December 2001 33A, 100V, 0.040 Ohm, N-Channel, UltraFET® Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN (FLANGE) • Ultra Low On-Resistance GATE - rDS(ON) = 0.040Ω, VGS = 10V GATE • Simulation Models SOURCE - Temperature Compensated PSPICE® and SABER™ Electrical Models DRAIN (FLANGE) - Spice an

4.4. huf75637s3 huf75637s3st.pdf Size:200K _update_mosfet

HUF75617D3
HUF75617D3

HUF75637P3, HUF75637S3S Data Sheet December 2001 44A, 100V, 0.030 Ohm, N-Channel, UltraFET® Power MOSFET Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN (FLANGE) • Ultra Low On-Resistance GATE - rDS(ON) = 0.030Ω, VGS = 10V GATE • Simulation Models SOURCE - Temperature Compensated PSPICE® and SABER™ Electrical Models DRAIN (FLANGE) - Spice and S

 4.5. huf75639s3st.pdf Size:227K _update_mosfet

HUF75617D3
HUF75617D3

HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Data Sheet December 2001 56A, 100V, 0.025 Ohm, N-Channel Features UltraFET Power MOSFETs • 56A, 100V These N-Channel power MOSFETs • Simulation Models are manufactured using the - Temperature Compensated PSPICE® and SABER™ innovative UltraFET® process. This Electrical Models advanced process technology - Spice and Saber T

4.6. huf75645s3st.pdf Size:203K _update_mosfet

HUF75617D3
HUF75617D3

 HUF75645P3, HUF75645S3S Data Sheet December 2001 75A, 100V, 0.014 Ohm, N-Channel, UltraFET® Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN • Ultra Low On-Resistance (FLANGE) GATE - rDS(ON) = 0.014Ω, VGS = 10V GATE • Simulation Models - Temperature Compensated PSPICE® and SABER™ SOURCE Electrical Models DRAIN - Spice and Saber Th

4.7. huf75639g3 huf75639p3 huf75639s3s huf75639s3.pdf Size:229K _fairchild_semi

HUF75617D3
HUF75617D3

HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Data Sheet December 2001 56A, 100V, 0.025 Ohm, N-Channel Features UltraFET Power MOSFETs 56A, 100V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Electrical Models advanced process technology - Spice and Saber Thermal Impe

4.8. huf75631sk8.pdf Size:254K _fairchild_semi

HUF75617D3
HUF75617D3

 HUF75631SK8 Data Sheet December 2001 5.5A, 100V, 0.039 Ohm, N-Channel, UltraFET® Power MOSFET Packaging JEDEC MS-012AA Features BRANDING DASH • Ultra Low On-Resistance - rDS(ON) = 0.039Ω, VGS = 10V 5 • Simulation Models 1 - Temperature Compensated PSPICE® and SABER™ 2 Electrical Models 3 4 - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com Symbol

4.9. huf75652g3.pdf Size:195K _fairchild_semi

HUF75617D3
HUF75617D3

HUF75652G3 Data Sheet December 2001 75A, 100V, 0.008 Ohm, N-Channel UltraFET Power MOSFET Packaging JEDEC TO-247 Features SOURCE DRAIN Ultra Low On-Resistance GATE - rDS(ON) = 0.008?, VGS = 10V Simulation Models - Temperature Compensated PSPICE and SABER Electrical Models - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com DRAIN HUF75652G3 (TAB) Peak C

4.10. huf75631s3s.pdf Size:202K _fairchild_semi

HUF75617D3
HUF75617D3

HUF75631P3, HUF75631S3ST Data Sheet December 2001 33A, 100V, 0.040 Ohm, N-Channel, UltraFET Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN (FLANGE) Ultra Low On-Resistance GATE - rDS(ON) = 0.040?, VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER Electrical Models DRAIN (FLANGE) - Spice and SABER Therm

4.11. huf75637.pdf Size:201K _fairchild_semi

HUF75617D3
HUF75617D3

HUF75637P3, HUF75637S3S Data Sheet December 2001 44A, 100V, 0.030 Ohm, N-Channel, UltraFET® Power MOSFET Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN (FLANGE) • Ultra Low On-Resistance GATE - rDS(ON) = 0.030Ω, VGS = 10V GATE • Simulation Models SOURCE - Temperature Compensated PSPICE® and SABER™ Electrical Models DRAIN (FLANGE) - Spice and S

4.12. huf75645p3 huf75645s3s.pdf Size:204K _fairchild_semi

HUF75617D3
HUF75617D3

HUF75645P3, HUF75645S3S Data Sheet December 2001 75A, 100V, 0.014 Ohm, N-Channel, UltraFET Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN Ultra Low On-Resistance (FLANGE) GATE - rDS(ON) = 0.014?, VGS = 10V GATE Simulation Models - Temperature Compensated PSPICE and SABER SOURCE Electrical Models DRAIN - Spice and Saber Thermal Impedan

4.13. huf75639s f085a.pdf Size:230K _fairchild_semi

HUF75617D3
HUF75617D3

HUFA75639S3ST_F085A Data Sheet March 2012 56A, 100V, 0.025 Ohm, N-Channel Features UltraFET Power MOSFETs • 56A, 100V These N-Channel power MOSFETs • Peak Current vs Pulse Width Curve are manufactured using the • UIS Rating Curve innovative UltraFET® process. This advanced process technology • Related Literature achieves the lowest possible on-resistance per silicon ar

4.14. huf75623p3.pdf Size:98K _intersil

HUF75617D3
HUF75617D3

HUF75623P3 Data Sheet November 1999 File Number 4804 22A, 100V, 0.064 Ohm, N-Channel, UltraFET Power MOSFET Packaging Features JEDEC TO-220AB • Ultra Low On-Resistance - rDS(ON) = 0.064Ω, VGS = 10V SOURCE DRAIN • Simulation Models GATE - Temperature Compensated PSPICE® and SABER© Electrical Models - Spice and SABER© Thermal Impedance Models - www.intersil.com DRAIN (

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