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HUF76619D3ST MOSFET. Datasheet. Equivalente. Reemplazo. Hoja de especificaciones. Principales características

Número de Parte: HUF76619D3ST

Código: 76619D

Tipo de FET: MOSFET

Polaridad de transistor: N

ESPECIFICACIONES MÁXIMAS

Disipación total del dispositivo (Pd): 75 W

Tensión drenaje-fuente (Vds): 100 V

Tensión compuerta-fuente (Vgs): 16 V

Corriente continua de drenaje (Id): 18 A

Temperatura operativa máxima (Tj): 175 °C

CARACTERÍSTICAS ELÉCTRICAS

Tensión umbral compuerta-fuente Vgs(th): 3 V

Carga de compuerta (Qg): 24 nC

Tiempo de elevación (tr): 82 nS

Conductancia de drenaje-sustrato (Cd): 138 pF

Resistencia drenaje-fuente RDS(on): 0.085 Ohm

Empaquetado / Estuche: TO-252AA

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HUF76619D3ST Datasheet (PDF)

1.1. huf76619d3st.pdf Size:222K _update_mosfet

HUF76619D3ST
HUF76619D3ST

HUF76619D3, HUF76619D3S Data Sheet December 2001 18A, 100V, 0.087 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging JEDEC TO-251AA JEDEC TO-252AA Features • Ultra Low On-Resistance DRAIN DRAIN SOURCE (FLANGE) (FLANGE) - rDS(ON) = 0.085Ω, VGS = 10V DRAIN GATE - rDS(ON) = 0.087Ω, VGS = 5V GATE • Simulation Models SOURCE - Temperature Compensated PSPICE®

1.2. huf76619d3-s.pdf Size:220K _fairchild_semi

HUF76619D3ST
HUF76619D3ST

HUF76619D3, HUF76619D3S Data Sheet December 2001 18A, 100V, 0.087 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging JEDEC TO-251AA JEDEC TO-252AA Features • Ultra Low On-Resistance DRAIN DRAIN SOURCE (FLANGE) (FLANGE) - rDS(ON) = 0.085Ω, VGS = 10V DRAIN GATE - rDS(ON) = 0.087Ω, VGS = 5V GATE • Simulation Models SOURCE - Temperature Compensated PSPICE®

 4.1. huf76633s3st.pdf Size:216K _update_mosfet

HUF76619D3ST
HUF76619D3ST

HUF76633P3, HUF76633S3S Data Sheet December 2001 38A, 100V, 0.036 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB • Ultra Low On-Resistance DRAIN SOURCE (FLANGE) - rDS(ON) = 0.035Ω, VGS = 10V DRAIN GATE - rDS(ON) = 0.036Ω, VGS = 5V • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™ SOURCE El

4.2. huf76609d3st.pdf Size:218K _update_mosfet

HUF76619D3ST
HUF76619D3ST

HUF76609D3, HUF76609D3S Data Sheet December 2001 10A, 100V, 0.165 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-251AA JEDEC TO-252AA • Ultra Low On-Resistance DRAIN DRAIN - rDS(ON) = 0.160Ω, VGS = 10V SOURCE (FLANGE) (FLANGE) DRAIN GATE - rDS(ON) = 0.165Ω, VGS = 5V GATE • Simulation Models - Temperature Compensated PSPICE® and SABER™

 4.3. huf76629d3st.pdf Size:201K _update_mosfet

HUF76619D3ST
HUF76619D3ST

HUF76629D3, HUF76629D3S Data Sheet December 2001 20A, 100V, 0.054 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging JEDEC TO-251AA JEDEC TO-252AA Features • Ultra Low On-Resistance DRAIN SOURCE (FLANGE) - rDS(ON) = 0.052Ω, VGS = 10V DRAIN - rDS(ON) = 0.054Ω, VGS = 5V GATE • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™ SOURCE Elect

4.4. huf76609d3s.pdf Size:220K _fairchild_semi

HUF76619D3ST
HUF76619D3ST

HUF76609D3, HUF76609D3S Data Sheet December 2001 10A, 100V, 0.165 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging Features JEDEC TO-251AA JEDEC TO-252AA Ultra Low On-Resistance DRAIN DRAIN - rDS(ON) = 0.160?, VGS = 10V SOURCE (FLANGE) (FLANGE) DRAIN GATE - rDS(ON) = 0.165?, VGS = 5V GATE Simulation Models - Temperature Compensated PSPICE and SABER SOURCE Elec

 4.5. huf76633p3-s3s.pdf Size:223K _fairchild_semi

HUF76619D3ST
HUF76619D3ST

HUF76633P3, HUF76633S3S Data Sheet December 2001 38A, 100V, 0.036 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB • Ultra Low On-Resistance DRAIN SOURCE (FLANGE) - rDS(ON) = 0.035Ω, VGS = 10V DRAIN GATE - rDS(ON) = 0.036Ω, VGS = 5V • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™ SOURCE El

4.6. huf76645p3-s3s.pdf Size:218K _fairchild_semi

HUF76619D3ST
HUF76619D3ST

HUF76645P3, HUF76645S3S Data Sheet December 2001 75A, 100V, 0.015 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB • Ultra Low On-Resistance DRAIN SOURCE - rDS(ON) = 0.014Ω, VGS = 10V DRAIN (FLANGE) GATE - rDS(ON) = 0.015Ω, VGS = 5V • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™ SOURCE Elect

4.7. huf76639s3s.pdf Size:218K _fairchild_semi

HUF76619D3ST
HUF76619D3ST

HUF76639P3, HUF76639S3S Data Sheet December 2001 50A, 100V, 0.027 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB Ultra Low On-Resistance SOURCE DRAIN - rDS(ON) = 0.026?, VGS = 10V DRAIN (FLANGE) GATE - rDS(ON) = 0.027?, VGS = 5V Simulation Models GATE - Temperature Compensated PSPICE and SABER SOURCE Electrical Models

4.8. huf76633p3 f085.pdf Size:369K _fairchild_semi

HUF76619D3ST
HUF76619D3ST

HUF76633P3_F085 Data Sheet April 2012 38A, 100V, 0.036 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-220AB • Ultra Low On-Resistance - rDS(ON) = 0.035Ω, VGS = 10V SOURCE DRAIN - rDS(ON) = 0.036Ω, VGS = 5V GATE • Simulation Models - Temperature Compensated PSPICE® and SABER™ Electrical Models - Spice and SABER Thermal Impedance Model

4.9. huf76629d3-s.pdf Size:203K _fairchild_semi

HUF76619D3ST
HUF76619D3ST

HUF76629D3, HUF76629D3S Data Sheet December 2001 20A, 100V, 0.054 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging JEDEC TO-251AA JEDEC TO-252AA Features Ultra Low On-Resistance DRAIN SOURCE (FLANGE) - rDS(ON) = 0.052?, VGS = 10V DRAIN - rDS(ON) = 0.054?, VGS = 5V GATE Simulation Models GATE - Temperature Compensated PSPICE and SABER SOURCE Electriecal Models

4.10. huf76639s f085.pdf Size:244K _fairchild_semi

HUF76619D3ST
HUF76619D3ST

HUF76639S3ST_F085 July 2012 50A, 100V, 0.026 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-263AB • Ultra Low On-Resistance DRAIN - rDS(ON) = 0.026Ω, VGS = 10V (FLANGE) • Simulation Models - Temperature Compensated PSPICE® and SABER™ GATE Electrical Models SOURCE - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com •

4.11. huf76645s f085.pdf Size:303K _fairchild_semi

HUF76619D3ST
HUF76619D3ST

HUFA76645S3ST_F085 Data Sheet September 2010 75A, 100V, 0.015 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features • Ultra Low On-Resistance JEDEC TO-263AB - rDS(ON) = 0.014Ω, VGS = 10V - rDS(ON) = 0.015Ω, VGS = 5V DRAIN • Simulation Models (FLANGE) - Temperature Compensated PSPICE® and SABER™ Electrical Models GATE - Spice and SABER Thermal Imped

4.12. huf76639p3-s3s.pdf Size:223K _fairchild_semi

HUF76619D3ST
HUF76619D3ST

HUF76639P3, HUF76639S3S Data Sheet December 2001 50A, 100V, 0.027 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB • Ultra Low On-Resistance SOURCE DRAIN - rDS(ON) = 0.026Ω, VGS = 10V DRAIN (FLANGE) GATE - rDS(ON) = 0.027Ω, VGS = 5V • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™ SOURCE Ele

Otros transistores... HUF76419D3ST , HUF76419S3ST , HUF76429D3ST , HUF76429S3ST , HUF76437S3ST , HUF76439S3ST , HUF76445S3ST , HUF76609D3ST , IRF9530 , HUF76629D3ST , HUF76633S3ST , HUFA75307D3 , HUFA75307D3S , HUFA75307D3ST , HUFA75307P3 , HUFA75309D3 , HUFA75309D3S .

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