75329S Datasheet and Replacement

HUFA75329G3, HUFA75329P3, HUFA75329S3SData Sheet June 200249A, 55V, 0.024 Ohm, N-Channel UltraFET FeaturesPower MOSFETs 49A, 55VThese N-Channel power MOSFETs Ultra Low On-Resistance, rDS(ON) = 0.024are manufactured using the Temperature Compensating PSPICE and SABER innovative UltraFET process. This Modelsadvanced process technology - Available on th

HUF75329G3, HUF75329P3, HUF75329S3SData Sheet December 200149A, 55V, 0.024 Ohm, N-Channel UltraFET FeaturesPower MOSFETs 49A, 55VThese N-Channel power MOSFETs Ultra Low On-Resistance, rDS(ON) = 0.024are manufactured using the Temperature Compensating PSPICE and SABER innovative UltraFET process. This Modelsadvanced process technology - Available on t

HUF75329D3SData Sheet October 2013N-Channel UltraFET Power MOSFET Features55 V, 20 A, 26 m 20A, 55VThese N-Channel power MOSFETs are manufactured using Simulation Modelsthe innovative UltraFET process. This advanced process - Temperature Compensated PSPICE and SABER technology achieves the lowest possible on-resistance per Modelssilicon area, resulting in ou

HUF75329D3, HUF75329D3SData Sheet December 200120A, 55V, 0.026 Ohm, N-Channel UltraFET FeaturesPower MOSFETs 20A, 55VThese N-Channel power MOSFETs Simulation Modelsare manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Modelsadvanced process technology - SPICE and SABER Thermal Impedance Models achieves the

HUFA75329D3, HUFA75329D3SData Sheet June 1999 File Number 4426.420A, 55V, 0.026 Ohm, N-Channel UltraFET FeaturesPower MOSFETs 20A, 55VThese N-Channel power MOSFETs Simulation Modelsare manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Modelsadvanced process technology - SPICE and SABER Thermal Impedance Mode

HUF75329D3SData Sheet October 2013N-Channel UltraFET Power MOSFETFeatures55 V, 20 A, 26 m 20A, 55VThese N-Channel power MOSFETs are manufactured Simulation Modelsusing the innovative UltraFET process. This advanced - Temperature Compensated PSPICE and SABER process technology achieves the lowest possible on-Modelsresistance per silicon area, resulting in o