All MOSFET. APT1001R6BN Datasheet

 

APT1001R6BN Datasheet and Replacement


   Type Designator: APT1001R6BN
   Type of Transistor: MOSFET
   Type of Control Channel: N -Channel
   Pd ⓘ - Maximum Power Dissipation: 240 W
   |Vds|ⓘ - Maximum Drain-Source Voltage: 1000 V
   |Vgs|ⓘ - Maximum Gate-Source Voltage: 30 V
   |Id| ⓘ - Maximum Drain Current: 8 A
   Tj ⓘ - Maximum Junction Temperature: 150 °C
   Qg ⓘ - Total Gate Charge: 66 nC
   tr ⓘ - Rise Time: 13 nS
   Cossⓘ - Output Capacitance: 230 pF
   Rds ⓘ - Maximum Drain-Source On-State Resistance: 1.6 Ohm
   Package: TO247
 

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APT1001R6BN Datasheet (PDF)

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APT1001R6BN

DTO-247GAPT1001R6BN 1000V 8.0A 1.60SAPT1002R4BN 1000V 6.5A 2.40POWER MOS IVN- CHANNEL ENHANCEMENT MODE HIGH VOLTAGE POWER MOSFETSMAXIMUM RATINGS All Ratings: TC = 25C unless otherwise specified.APT APTSymbol Parameter 1001R6BN 1002R4BN UNITVDSS Drain-Source Voltage1000 1000 VoltsID Continuous Drain Current @ TC = 25C8 6.5AmpsIDM Pulsed Drain Current 1

 4.1. Size:150K  apt
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APT1001R6BN

Typical Performance CurvesAPT1001R6BFLL_SFLLAPT1001R6BFLLAPT1001R6SFLL1000V 8A 1.60R POWER MOS 7 FREDFETD3PAKPower MOS 7 is a new generation of low loss, high voltage, N-ChannelTO-247enhancement mode power MOSFETS. Both conduction and switchinglosses are addressed with Power MOS 7 by significantly lowering RDS(ON)and Qg. Power MOS 7 combines

 6.1. Size:68K  apt
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APT1001R6BN

APT1001R1AVR1000V 9A 1.100POWER MOS VTO-3Power MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout.D Faster Switching 100% Avalanche Tested Lower

 6.2. Size:34K  apt
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APT1001R6BN

APT1001RBLCAPT1001RSLC1000V 11A 1.000WBLCTMPOWER MOS VID3PAKPower MOS VITM is a new generation of low gate charge, high voltageTO-247N-Channel enhancement mode power MOSFETs. Lower gate charge isachieved by optimizing the manufacturing process to minimize Ciss and Crss.Lower gate charge coupled with Power MOS VITM optimized gate layout,SLCdelivers exceptionally fast sw

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History: SML100J34

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