APT10050JVFR
MOSFET. Datasheet pdf. Equivalent
Type Designator: APT10050JVFR
Type of Transistor: MOSFET
Type of Control Channel: N
-Channel
Pdⓘ
- Maximum Power Dissipation: 450
W
|Vds|ⓘ - Maximum Drain-Source Voltage: 1000
V
|Vgs|ⓘ - Maximum Gate-Source Voltage: 30
V
|Id|ⓘ - Maximum Drain Current: 19
A
Tjⓘ - Maximum Junction Temperature: 150
°C
Qgⓘ - Total Gate Charge: 335
nC
trⓘ - Rise Time: 13
nS
Cossⓘ -
Output Capacitance: 595
pF
Rdsⓘ - Maximum Drain-Source On-State Resistance: 0.5
Ohm
Package:
SOT227
APT10050JVFR
Transistor Equivalent Substitute - MOSFET Cross-Reference Search
APT10050JVFR
Datasheet (PDF)
..1. Size:71K apt
apt10050jvfr.pdf
APT10050JVFR1000V 19A 0.500POWER MOS V FREDFETPower MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout."UL Recognized"ISOTOP Fast Recovery Body Diode
4.1. Size:68K apt
apt10050jvr.pdf
APT10050JVR1000V 19A 0.500POWER MOS VPower MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout."UL Recognized"ISOTOP Faster Switching 100% Avalanche
5.1. Size:60K apt
apt10050jn.pdf
DGAPT10050JN 1000V 20.5A 0.50SISOTOP"UL Recognized" File No. E145592 (S)POWER MOS IVSINGLE DIE ISOTOP PACKAGEN- CHANNEL ENHANCEMENT MODE HIGH VOLTAGE POWER MOSFETSMAXIMUM RATINGS All Ratings: TC = 25C unless otherwise specified.APTSymbol Parameter 10050JN UNITVDSS Drain-Source Voltage1000 VoltsID Continuous Drain Current @ TC = 25C20.5AmpsIDM, lLM
5.2. Size:39K apt
apt10050jlc.pdf
APT10050JLC1000V 19A 0.500TMPOWER MOS VIPower MOS VITM is a new generation of low gate charge, high voltageN-Channel enhancement mode power MOSFETs. Lower gate charge isachieved by optimizing the manufacturing process to minimize Ciss and Crss.Lower gate charge coupled with Power MOS VITM optimized gate layout,"UL Recognized"delivers exceptionally fast s
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