HUF75637S3ST - описание и поиск аналогов

 ..1. Size:200K  fairchild semi
 huf75637s3 huf75637s3st.pdf 

HUF75637P3, HUF75637S3S Data Sheet December 2001 44A, 100V, 0.030 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN (FLANGE) Ultra Low On-Resistance GATE - rDS(ON) = 0.030 , VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER Electrical Models DRAIN (FLANGE) - Spice and S

 6.1. Size:201K  fairchild semi
 huf75637.pdf 

HUF75637P3, HUF75637S3S Data Sheet December 2001 44A, 100V, 0.030 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN (FLANGE) Ultra Low On-Resistance GATE - rDS(ON) = 0.030 , VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER Electrical Models DRAIN (FLANGE) - Spice and S

 7.1. Size:227K  fairchild semi
 huf75639s3st.pdf 

HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Data Sheet December 2001 56A, 100V, 0.025 Ohm, N-Channel Features UltraFET Power MOSFETs 56A, 100V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Electrical Models advanced process technology - Spice and Saber T

 7.2. Size:254K  fairchild semi
 huf75631sk8.pdf 

HUF75631SK8 Data Sheet December 2001 5.5A, 100V, 0.039 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC MS-012AA Features BRANDING DASH Ultra Low On-Resistance - rDS(ON) = 0.039 , VGS = 10V 5 Simulation Models 1 - Temperature Compensated PSPICE and SABER 2 Electrical Models 3 4 - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com Symbol

 7.3. Size:230K  fairchild semi
 huf75639s f085a.pdf 

HUFA75639S3ST_F085A Data Sheet March 2012 56A, 100V, 0.025 Ohm, N-Channel Features UltraFET Power MOSFETs 56A, 100V These N-Channel power MOSFETs Peak Current vs Pulse Width Curve are manufactured using the UIS Rating Curve innovative UltraFET process. This advanced process technology Related Literature achieves the lowest possible on-resistance per silicon ar

 7.4. Size:202K  fairchild semi
 huf75631s3s.pdf 

HUF75631P3, HUF75631S3ST Data Sheet December 2001 33A, 100V, 0.040 Ohm, N-Channel, UltraFET Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN (FLANGE) Ultra Low On-Resistance GATE - rDS(ON) = 0.040 , VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER Electrical Models DRAIN (FLANGE) - Spice an

 7.5. Size:249K  fairchild semi
 huf75631sk8t.pdf 

HUF75631SK8 Data Sheet December 2001 5.5A, 100V, 0.039 Ohm, N-Channel, UltraFET Power MOSFET Packaging JEDEC MS-012AA Features BRANDING DASH Ultra Low On-Resistance - rDS(ON) = 0.039 , VGS = 10V 5 Simulation Models 1 - Temperature Compensated PSPICE and SABER 2 Electrical Models 3 4 - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com Symbol

 7.6. Size:229K  fairchild semi
 huf75639g3 huf75639p3 huf75639s3s huf75639s3.pdf 

HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Data Sheet December 2001 56A, 100V, 0.025 Ohm, N-Channel Features UltraFET Power MOSFETs 56A, 100V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Electrical Models advanced process technology - Spice and Saber T

 7.7. Size:200K  fairchild semi
 huf75631s3st.pdf 

HUF75631P3, HUF75631S3ST Data Sheet December 2001 33A, 100V, 0.040 Ohm, N-Channel, UltraFET Power MOSFETs Packaging JEDEC TO-220AB JEDEC TO-263AB Features SOURCE DRAIN DRAIN (FLANGE) Ultra Low On-Resistance GATE - rDS(ON) = 0.040 , VGS = 10V GATE Simulation Models SOURCE - Temperature Compensated PSPICE and SABER Electrical Models DRAIN (FLANGE) - Spice an

 7.8. Size:720K  onsemi
 huf75639g3 huf75639p3 huf75639s3s huf75639s3.pdf 

MOSFET Power, N-Channel, Ultrafet 100 V, 56 A, 25 mW HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 www.onsemi.com These N-Channel power MOSFETs are manufactured using the innovative Ultrafet process. This advanced process technology achieves the lowest possible on- resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high ener