October 2000PRELIMINARYFDG6308PP-Channel 1.8V Specified PowerTrench MOSFETGeneral Description FeaturesThis P-Channel 1.8V specified MOSFET uses 0.6 A, 20 V. RDS(ON) = 0.40 @ VGS = 4.5 VFairchilds advanced low voltage PowerTrench process.RDS(ON) = 0.55 @ VGS = 2.5 VIt has been optimized for battery power managementRDS(ON) = 0.80

March 2009 FDG6301N_F085 Dual N-Channel, Digital FETGeneral Description Features25 V, 0.22 A continuous, 0.65 A peak.These dual N-Channel logic level enhancement modefield effect transistors are produced using Fairchild's RDS(ON) = 4 @ VGS= 4.5 V,proprietary, high cell density, DMOS technology. ThisRDS(ON) = 5 @ VGS= 2.7 V.very high density process is especially tailor

July 1999 FDG6301N Dual N-Channel, Digital FETGeneral Description Features25 V, 0.22 A continuous, 0.65 A peak.These dual N-Channel logic level enhancement modefield effect transistors are produced using Fairchild's RDS(ON) = 4 @ VGS= 4.5 V,proprietary, high cell density, DMOS technology. ThisRDS(ON) = 5 @ VGS= 2.7 V.very high density process is especially tailored to

February 2001 FDG6306P P-Channel 2.5V Specified PowerTrench MOSFET General Description Features This P 2.5V specified MOSFET is a rugged -Channel 0.6 A, 20 V. R = 420 m @ V = 4.5 V DS(ON) GSgate version of Fairchild Semiconductors advanced R = 630 m @ V = 2.5 V DS(ON) GSPowerTrench process. It has been optimized for power management applications

September 2001 FDG6303N Dual N-Channel, Digital FETGeneral Description Features25 V, 0.50 A continuous, 1.5 A peak.These dual N-Channel logic level enhancement mode RDS(ON) = 0.45 @ VGS= 4.5 V,field effect transistors are produced using Fairchild'sproprietary, high cell density, DMOS technology. This RDS(ON) =0.60 @ VGS= 2.7 V.very high density process is especially ta

July 1999 FDG6304P Dual P-Channel, Digital FETGeneral Description Features-25 V, -0.41 A continuous, -1.5 A peak.These dual P-Channel logic level enhancement mode RDS(ON) = 1.1 @ VGS= -4.5 V,field effect transistors are produced using Fairchild'sproprietary, high cell density, DMOS technology. ThisRDS(ON) = 1.5 @ VGS= -2.7 V.very high density process is especially ta

July 1999 FDG6302P Dual P-Channel, Digital FETGeneral Description Features-25 V, -0.14 A continuous, -0.4 A peak.These dual P-Channel logic level enhancement mode RDS(ON) = 10 @ VGS= -4.5 V,field effect transistors are produced using Fairchild'sproprietary, high cell density, DMOS technology. ThisRDS(ON) = 13 @ VGS= -2.7 V.very high density process is especially tail

Digital FET, Dual N-ChannelFDG6301NGeneral DescriptionThese dual N-Channel logic level enhancement mode field effecttransistors are produced using ON Semiconductors proprietary, highcell density, DMOS technology. This very high density process iswww.onsemi.comespecially tailored to minimize on-state resistance. This device hasbeen designed especially for low voltage applicati

FDG6303N Dual N-Channel, Digital FETGeneral Description Features25 V, 0.50 A continuous, 1.5 A peak.These dual N-Channel logic level enhancement mode RDS(ON) = 0.45 @ VGS= 4.5 V,field effect transistors are produced using ON Semiconductor's proprietary, high cell density, DMOS RDS(ON) =0.60 @ VGS= 2.7 V.technology. This very high density process is Very low level gate

SMD Type MOSFETDual N-Channel MOSFETFDG6301N (KDG6301N) Features VDS (V) = 25V ID = 220m A (VGS = 4.5V) RDS(ON) 4 (VGS = 4.5V) RDS(ON) 5 (VGS = 2.7V) Gate-Source Zener for ESD ruggedness1 S1 S1 4 S2(>6kV Human Body Model).2 G12 G1 5 G23 D2 3 D2 6 D1 1 or 4 6 or 3 2 or 5 5 or 24 or 1 3 or 6 Absolute Maximum Ratings T

FDG6303Nwww.VBsemi.twDual N-Channel 20 V (D-S) MOSFETFEATURESPRODUCT SUMMARY Halogen-free According to IEC 61249-2-21VDS (V) RDS(on) ()ID (A)a Qg (Typ.) Definition TrenchFET Power MOSFET0.086 at VGS = 4.5 V 2.6a 100 % Rg Tested20 0.110 at VGS = 2.5 V 2.5a 5.0 nC Typical ESD Protection 2100 V HBMa0.180 at VGS = 1.8 V 2.3 Compliant to RoHS Directive