75329P Todos los transistores

HUFA75329G3, HUFA75329P3, HUFA75329S3S Data Sheet June 2002 49A, 55V, 0.024 Ohm, N-Channel UltraFET Features Power MOSFETs 49A, 55V These N-Channel power MOSFETs Ultra Low On-Resistance, rDS(ON) = 0.024 are manufactured using the Temperature Compensating PSPICE and SABER innovative UltraFET process. This Models advanced process technology - Available on th

HUF75329G3, HUF75329P3, HUF75329S3S Data Sheet December 2001 49A, 55V, 0.024 Ohm, N-Channel UltraFET Features Power MOSFETs 49A, 55V These N-Channel power MOSFETs Ultra Low On-Resistance, rDS(ON) = 0.024 are manufactured using the Temperature Compensating PSPICE and SABER innovative UltraFET process. This Models advanced process technology - Available on t

HUF75329D3S Data Sheet October 2013 N-Channel UltraFET Power MOSFET Features 55 V, 20 A, 26 m 20A, 55V These N-Channel power MOSFETs are manufactured using Simulation Models the innovative UltraFET process. This advanced process - Temperature Compensated PSPICE and SABER technology achieves the lowest possible on-resistance per Models silicon area, resulting in ou

HUF75329D3, HUF75329D3S Data Sheet December 2001 20A, 55V, 0.026 Ohm, N-Channel UltraFET Features Power MOSFETs 20A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Models advanced process technology - SPICE and SABER Thermal Impedance Models achieves the

HUFA75329D3, HUFA75329D3S Data Sheet June 1999 File Number 4426.4 20A, 55V, 0.026 Ohm, N-Channel UltraFET Features Power MOSFETs 20A, 55V These N-Channel power MOSFETs Simulation Models are manufactured using the - Temperature Compensated PSPICE and SABER innovative UltraFET process. This Models advanced process technology - SPICE and SABER Thermal Impedance Mode

HUF75329D3S Data Sheet October 2013 N-Channel UltraFET Power MOSFET Features 55 V, 20 A, 26 m 20A, 55V These N-Channel power MOSFETs are manufactured Simulation Models using the innovative UltraFET process. This advanced - Temperature Compensated PSPICE and SABER process technology achieves the lowest possible on- Models resistance per silicon area, resulting in o