FDG315N Todos los transistores

 ..1. Size:81K  fairchild semi
 fdg315n.pdf

July 2000 FDG315N N-Channel Logic Level PowerTrench MOSFET General Description Features This N-Channel Logic Level MOSFET is produced using 2 A, 30 V. RDS(ON) = 0.12 @ VGS = 10 V Fairchild Semiconductor's advanced PowerTrench RDS(ON) = 0.16 @ VGS = 4.5 V. process that has been especially tailored to minimize on-state resistance and yet maintain super

 9.1. Size:80K  fairchild semi
 fdg313n d87z.pdf

July 2000 FDG313N Digital FET, N-Channel General Description Features This N-Channel enhancement mode field effect 0.95 A, 25 V. RDS(on) = 0.45 @ VGS = 4.5 V transistor is produced using Fairchild's proprietary, high RDS(on) = 0.60 @ VGS = 2.7 V. cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This devic

 9.2. Size:89K  fairchild semi
 fdg311n.pdf

February 2000 FDG311N N-Channel 2.5V Specified PowerTrench MOSFET General Description Features This N-Channel MOSFET is produced using Fairchild 1.9 A, 20 V. RDS(ON) = 0.115 @ VGS = 4.5 V Semiconductor's advanced PowerTrench process that RDS(ON) = 0.150 @ VGS = 2.5 V. has been especially tailored to minimize the on-state resistance and yet maintain lo

 9.3. Size:82K  fairchild semi
 fdg313n.pdf

July 2000 FDG313N Digital FET, N-Channel General Description Features This N-Channel enhancement mode field effect 0.95 A, 25 V. RDS(on) = 0.45 @ VGS = 4.5 V transistor is produced using Fairchild's proprietary, high RDS(on) = 0.60 @ VGS = 2.7 V. cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This devic

 9.4. Size:79K  fairchild semi
 fdg312p.pdf

February 1999 FDG312P P-Channel 2.5V Specified PowerTrench MOSFET General Description Features This P-Channel MOSFET is produced using Fairchild -1.2 A, -20 V. RDS(on) = 0.18 @ VGS = -4.5 V Semiconductor's advanced PowerTrench process that RDS(on) = 0.25 @ VGS = -2.5 V. has been especially tailored to minimize the on-state resistance and yet maintain low gate charge for

 9.5. Size:70K  fairchild semi
 fdg316p.pdf

December 2001 FDG316P P-Channel Logic Level PowerTrench MOSFET General Description Features This P-Channel Logic Level MOSFET is produced using -1.6 A, -30 V. RDS(ON) = 0.19 @ VGS = -10 V Fairchild Semiconductor's advanced PowerTrench RDS(ON) = 0.30 @ VGS = -4.5 V. process that has been especially tailored to minimize on-state resistance and yet maint

 9.6. Size:84K  fairchild semi
 fdg314p.pdf

July 2000 FDG314P Digital FET, P-Channel General Description Features This P-Channel enhancement mode field effect -0.65 A, -25 V. RDS(ON) = 1.1 @ VGS = -4.5 V transistor is produced using Fairchild Semiconductor s RDS(ON) = 1.5 @ VGS = -2.7 V. proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on- state resistance at

 9.7. Size:201K  onsemi
 fdg311n.pdf

Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclatur

 9.8. Size:185K  onsemi
 fdg316p.pdf

Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclatur