ST1002 MOSFET Equivalente. Reemplazo. Hoja de especificaciones. Principales características

Número de Parte: ST1002

Tipo de FET: MOSFET

Polaridad de transistor: N

ESPECIFICACIONES MÁXIMAS

Pdⓘ - Máxima disipación de potencia: 2 W

|Vds|ⓘ - Voltaje máximo drenador-fuente: 100 V

|Vgs|ⓘ - Voltaje máximo fuente-puerta: 20 V

|Id|ⓘ - Corriente continua de drenaje: 5 A

Tjⓘ - Temperatura máxima de unión: 150 °C

CARACTERÍSTICAS ELÉCTRICAS

trⓘ - Tiempo de subida: 10 nS

Cossⓘ - Capacitancia de salida: 160 pF

RDSonⓘ - Resistencia estado encendido drenaje a fuente: 0.135 Ohm

Encapsulados: SOT-23

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ST1002 datasheet

 ..1. Size:716K  stansontech
 st1002.pdf pdf_icon

ST1002

ST1002 N Channel Enhancement Mode MOSFET 3.0A DESCRIPTION The ST1002 is the N-Channel logic enhancement mode power field effect transistor is produce using high cell density, DMOS trench technology. This high-density process is especially tailored to minimize on-state resistance. These device are particularly suited for low voltage application such as cellular phone and notebo

 9.1. Size:67K  philips
 bst100.pdf pdf_icon

ST1002

DISCRETE SEMICONDUCTORS DATA SHEET BST100 P-channel enhancement mode vertical D-MOS transistor April 1995 Product specification File under Discrete Semiconductors, SC13b Philips Semiconductors Product specification P-channel enhancement mode vertical BST100 D-MOS transistor DESCRIPTION QUICK REFERENCE DATA P-channel vertical D-MOS transistor Drain-source voltage -VDS max. 60 V T

 9.2. Size:1277K  stansontech
 st1004srg.pdf pdf_icon

ST1002

ST1004SRG N Channel Enhancement Mode MOSFET 2.0A DESCRIPTION ST1004SRG is the N-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. The process is especially to improve the overall efficiency of DC/DC conventional switching PWM controllers. It has been optimized for low gate charge, low R and fast switchi

 9.3. Size:657K  stansontech
 st1005srg.pdf pdf_icon

ST1002

ST1005SRG P Channel Enhancement Mode MOSFET -0.8A DESCRIPTION ST1005SRG is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone an

MOSTRAR MÁS

Otros transistores... SRM7N65DTR-E1, SRM7N65TF-E1, SRM7N65TC-E1, SS05N70, SS07N70, SSD80N03, SSFM2506L, SSFM2508, IRFZ44, ST1004SRG, ST1005SRG, ST10E4, ST12N10D, ST13P10, ST2300, ST2300SRG, ST2301A