APT1001RSVRG MOSFET. Datasheet. Equivalente. Reemplazo. Hoja de especificaciones. Principales características
Número de Parte: APT1001RSVRG
Tipo de FET: MOSFET
Polaridad de transistor: N
ESPECIFICACIONES MÁXIMAS
Pdⓘ - Máxima disipación de potencia: 280 W|Vds|ⓘ - Voltaje máximo drenador - fuente: 1000 V
|Vgs|ⓘ - Voltaje máximo fuente - puerta: 30 V
|Id|ⓘ - Corriente continua de drenaje: 11 A
Tjⓘ - Temperatura máxima de unión: 150 °C
CARACTERÍSTICAS ELÉCTRICAS
|Vgs(th)|ⓘ - Tensión umbral entre puerta y fuente: 4 VQgⓘ - Carga de la puerta: 150 nC
trⓘ - Tiempo de subida: 11 nS
Cossⓘ - Capacitancia de salida: 280 pF
Rds(on)ⓘ - Resistencia estado encendido drenaje a fuente: 1 Ohm
Paquete / Cubierta: D3PAK
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APT1001RSVRG Datasheet (PDF)
apt1001rsvrg.pdf
APT1001RSVR1000V 11A 1.000POWER MOS VD3PAKPower MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout.D Faster Switching 100% Avalanche Tested Lowe
apt1001rsvr.pdf
APT1001RSVR1000V 11A 1.000POWER MOS VD3PAKPower MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout.D Faster Switching 100% Avalanche Tested Lowe
apt1001rsvfr.pdf
APT1001RBVFRAPT1001RSVFR1000V 11A 1.00BVFR POWER MOS V FREDFETD3PAKTO-247Power MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS VSVFRalso achieves faster switching speeds through optimized gate layou
apt1001rslc.pdf
APT1001RBLCAPT1001RSLC1000V 11A 1.000WBLCTMPOWER MOS VID3PAKPower MOS VITM is a new generation of low gate charge, high voltageTO-247N-Channel enhancement mode power MOSFETs. Lower gate charge isachieved by optimizing the manufacturing process to minimize Ciss and Crss.Lower gate charge coupled with Power MOS VITM optimized gate layout,SLCdelivers exceptionally fast sw
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