APT1001RSVRG
MOSFET. Datasheet pdf. Equivalent
Type Designator: APT1001RSVRG
Type of Transistor: MOSFET
Type of Control Channel: N
-Channel
Pdⓘ
- Maximum Power Dissipation: 280
W
|Vds|ⓘ - Maximum Drain-Source Voltage: 1000
V
|Vgs|ⓘ - Maximum Gate-Source Voltage: 30
V
|Vgs(th)|ⓘ - Maximum Gate-Threshold Voltage: 4
V
|Id|ⓘ - Maximum Drain Current: 11
A
Tjⓘ - Maximum Junction Temperature: 150
°C
Qgⓘ - Total Gate Charge: 150
nC
trⓘ - Rise Time: 11
nS
Cossⓘ -
Output Capacitance: 280
pF
Rdsⓘ - Maximum Drain-Source On-State Resistance: 1
Ohm
Package:
D3PAK
APT1001RSVRG
Transistor Equivalent Substitute - MOSFET Cross-Reference Search
APT1001RSVRG
Datasheet (PDF)
..1. Size:63K apt
apt1001rsvrg.pdf
APT1001RSVR1000V 11A 1.000POWER MOS VD3PAKPower MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout.D Faster Switching 100% Avalanche Tested Lowe
3.1. Size:71K apt
apt1001rsvr.pdf
APT1001RSVR1000V 11A 1.000POWER MOS VD3PAKPower MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout.D Faster Switching 100% Avalanche Tested Lowe
4.1. Size:139K apt
apt1001rsvfr.pdf
APT1001RBVFRAPT1001RSVFR1000V 11A 1.00BVFR POWER MOS V FREDFETD3PAKTO-247Power MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS VSVFRalso achieves faster switching speeds through optimized gate layou
5.1. Size:34K apt
apt1001rslc.pdf
APT1001RBLCAPT1001RSLC1000V 11A 1.000WBLCTMPOWER MOS VID3PAKPower MOS VITM is a new generation of low gate charge, high voltageTO-247N-Channel enhancement mode power MOSFETs. Lower gate charge isachieved by optimizing the manufacturing process to minimize Ciss and Crss.Lower gate charge coupled with Power MOS VITM optimized gate layout,SLCdelivers exceptionally fast sw
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