STU428S Todos los transistores

 

STU428S MOSFET. Datasheet. Equivalente. Reemplazo. Hoja de especificaciones. Principales características


   Número de Parte: STU428S
   Tipo de FET: MOSFET
   Polaridad de transistor: N

ESPECIFICACIONES MÁXIMAS

   Pdⓘ - Máxima disipación de potencia: 50 W
   |Vds|ⓘ - Voltaje máximo drenador - fuente: 40 V
   |Vgs|ⓘ - Voltaje máximo fuente - puerta: 20 V
   |Id|ⓘ - Corriente continua de drenaje: 50 A

CARACTERÍSTICAS ELÉCTRICAS


   Cossⓘ - Capacitancia de salida: 220 pF
   Rds(on)ⓘ - Resistencia estado encendido drenaje a fuente: 0.01 Ohm
   Paquete / Cubierta: TO252 DPAK

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STU428S Datasheet (PDF)

 ..1. Size:94K  samhop
stu428s std428s.pdf

STU428S
STU428S

S TU/D428SS amHop Microelectronics C orp.Mar.8,2007N-Channel Logic Level E nhancement Mode Field E ffect TransistorFEATUR ESPR ODUCT S UMMAR YS uper high dense cell design for low R DS (ON).TypVDS S ID R DS (ON) ( m )R ugged and reliable.8 @ VGS =10VSurface Mount Package.40V 50A10 @ VGS =4.5VESD Protected.DDGGSSTU SERIES STD SERIESTO-252AA(D-PAK) TO-

 9.1. Size:113K  samhop
stu426s std426s.pdf

STU428S
STU428S

S TU/D426SS amHop Microelectronics C orp.Oct,2007 ver1.1N-Channel Logic Level E nhancement Mode Field E ffect TransistorPR ODUCT S UMMAR Y FEATUR ESS uper highdense cell design for lowR DS (ON).TypVDS S ID R DS (ON) ( m )R ugged and reliable.8 @ VGS =10V40V 53ATO-252 and TO-251 Package.10 @ VGS =4.5VDDGSGSTU SERIES STD SERIESTO-252AA(D-PAK) TO-251(l-PAK)

 9.2. Size:119K  samhop
stu421s std421s.pdf

STU428S
STU428S

GreenProductSTU/D421SSamHop Microelectronics Corp.Aug.20,2006P-Channel Logic Level Enhancement Mode Field Effect TransistorPRODUCT SUMMARY FEATURESRDS(ON) ( m ) MaxVDSS ID Super high dense cell design for low RDS(ON).Rugged and reliable.45 @ VGS = -10V-40V -10ATO-252 and TO-251 Package.60 @ VGS = -4.5VDDDGGGSSSTU SERIES STD SERIESTO-252AA(D-PAK)

 9.3. Size:91K  samhop
stu420s std420s.pdf

STU428S
STU428S

S TU/D420SS amHop Microelectronics C orp.July 05,2006N-Channel Logic Level E nhancement Mode Field E ffect TransistorPR ODUC T S UMMAR Y FEATUR ESS uper high dense cell design for low R DS (ON).VDS S ID R DS (ON) ( m ) MaxR ugged and reliable.24 @ VGS = 10V24A40VTO-252 and TO-251 Package.30 @ VGS =4.5VDDGSGSTU SERIES STD SERIESTO-252AA(D-PAK) TO-251(l-PA

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