FDG6320C Todos los transistores

November 1998 FDG6320C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 @ VGS= 4.5 V, field effect transistors are produced using Fairchild's RDS(ON) = 5.0 @ VGS= 2.7 V. proprietary, high cell density, DMOS technology. This very high density process is especially tailored to mi

June 2008 FDG6322C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 @ VGS= 4.5 V, field effect transistors are produced using Fairchild's RDS(ON) = 5.0 @ VGS= 2.7 V. proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimiz

November 1998 FDG6321C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode field N-Ch 0.50 A, 25 V, RDS(ON) = 0.45 @ VGS= 4.5V. effect transistors are produced using Fairchild's proprietary, RDS(ON) = 0.60 @ VGS= 2.7 V. high cell density, DMOS technology. This very high density process is especially tailored to mi

FDG6322C Features Dual N & P Channel Digital FET N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 @ VGS= 4.5 V, RDS(ON) = 5.0 @ VGS= 2.7 V. General Description P-Ch -0.41 A,-25V, RDS(ON) = 1.1 @ VGS= -4.5V, These dual N & P-Channel logic level enhancement mode RDS(ON) = 1.5 @ VGS= -2.7V. field effect transistors are produced using ON Semiconductor's proprietary, high cell densit

Digital FET, Dual N & P Channel FDG6321C General Description These dual N & P-Channel logic level enhancement mode field www.onsemi.com effect transistors are produced using ON Semiconductor s proprietary, high cell density, DMOS technology. This very high density process is S2 especially tailored to minimize on-state resistance. This device has G2 D1 been designed especially on l