FDV305N Todos los transistores

 

FDV305N MOSFET Equivalente. Reemplazo. Hoja de especificaciones. Principales características

Número de Parte: FDV305N

Tipo de FET: MOSFET

Polaridad de transistor: N

ESPECIFICACIONES MÁXIMAS

Pdⓘ - Máxima disipación de potencia: 0.35 W

|Vds|ⓘ - Voltaje máximo drenador-fuente: 20 V

|Vgs|ⓘ - Voltaje máximo fuente-puerta: 12 V

|Id|ⓘ - Corriente continua de drenaje: 0.9 A

Tjⓘ - Temperatura máxima de unión: 150 °C

CARACTERÍSTICAS ELÉCTRICAS

RDSonⓘ - Resistencia estado encendido drenaje a fuente: 0.22 Ohm

Encapsulados: SOT23 SUPERSOT3

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FDV305N datasheet

 ..1. Size:172K  fairchild semi
fdv305n.pdf pdf_icon

FDV305N

January 2003 FDV305N 20V N-Channel PowerTrench MOSFET General Description Features This 20V N-Channel MOSFET uses Fairchild s high 0.9 A, 20 V RDS(ON) = 220 m @ VGS = 4.5 V voltage PowerTrench process. It has been optimized for RDS(ON) = 300 m @ VGS = 2.5 V power management applications. Low gate charge Applications Fast switching speed Load s

 ..2. Size:289K  onsemi
fdv305n.pdf pdf_icon

FDV305N

Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclatur

 9.1. Size:47K  fairchild semi
fdv303n nb9u008.pdf pdf_icon

FDV305N

August 1997 FDV303N Digital FET, N-Channel General Description Features 25 V, 0.68 A continuous, 2 A Peak. These N-Channel enhancement mode field effect transistors are RDS(ON) = 0.45 @ VGS = 4.5 V produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize RDS(ON) = 0.6 @ VGS= 2.7 V. on-state resistanc

 9.2. Size:173K  fairchild semi
fdv301n d87z fdv301n nb9v005.pdf pdf_icon

FDV305N

June 2009 FDV301N Digital FET , N-Channel General Description Features 25 V, 0.22 A continuous, 0.5 A Peak. This N-Channel logic level enhancement mode field effect RDS(ON) = 5 @ VGS= 2.7 V transistor is produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is RDS(ON) = 4 @ VGS= 4.5 V. especially tailored to minimize on-

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