APT5020BVR Datasheet and Replacement

APT5020BVR500V 26A 0.200POWER MOS VPower MOS V is a new generation of high voltage N-Channel enhancement TO-247mode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout. Faster Switching 100% Avalanche Tested D Lower L

isc N-Channel MOSFET Transistor APT5020BVRFEATURESDrain Current I =26A@ T =25D CDrain Source Voltage-: V =500V(Min)DSSStatic Drain-Source On-Resistance: R =0.2(Max)DS(on)100% avalanche testedMinimum Lot-to-Lot variations for robust deviceperformance and reliable operationDESCRIPTIONDesigned for use in switch mode power supplies and generalpurpos

APT5020BVFR500V 26A 0.200POWER MOS V FREDFETPower MOS V is a new generation of high voltage N-Channel enhancement TO-247mode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout. Fast Recovery Body Diode 100% Avalanche Test

isc N-Channel MOSFET Transistor APT5020BVFRFEATURESDrain Current I =26A@ T =25D CDrain Source Voltage-: V =500V(Min)DSSStatic Drain-Source On-Resistance: R =0.2(Max)DS(on)100% avalanche testedMinimum Lot-to-Lot variations for robust deviceperformance and reliable operationDESCRIPTIONDesigned for use in switch mode power supplies and generalpurpo

DTO-247GAPT5020BN 500V 28.0A 0.20SAPT5022BN 500V 27.0A 0.22POWER MOS IVN- CHANNEL ENHANCEMENT MODE HIGH VOLTAGE POWER MOSFETSMAXIMUM RATINGS All Ratings: TC = 25C unless otherwise specified.APT APTSymbol Parameter 5020BN 5022BN UNITVDSS Drain-Source Voltage500 500 VoltsID Continuous Drain Current @ TC = 25C28 27AmpsIDM Pulsed Drain Current 1112 108

APT5020BLCAPT5020SLC500V 26A 0.200WBLCTMPOWER MOS VID3PAKPower MOS VITM is a new generation of low gate charge, high voltageTO-247N-Channel enhancement mode power MOSFETs. Lower gate charge isachieved by optimizing the manufacturing process to minimize Ciss and Crss.Lower gate charge coupled with Power MOS VITM optimized gate layout,SLCdelivers exceptionally fast switc