APT40M70B2VFRG
MOSFET. Datasheet pdf. Equivalent
Type Designator: APT40M70B2VFRG
Type of Transistor: MOSFET
Type of Control Channel: N
-Channel
Pdⓘ
- Maximum Power Dissipation: 520
W
|Vds|ⓘ - Maximum Drain-Source Voltage: 400
V
|Vgs|ⓘ - Maximum Gate-Source Voltage: 30
V
|Vgs(th)|ⓘ - Maximum Gate-Threshold Voltage: 4
V
|Id|ⓘ - Maximum Drain Current: 57
A
Tjⓘ - Maximum Junction Temperature: 150
°C
Qgⓘ - Total Gate Charge: 330
nC
trⓘ - Rise Time: 16
nS
Cossⓘ -
Output Capacitance: 1140
pF
Rdsⓘ - Maximum Drain-Source On-State Resistance: 0.07
Ohm
Package:
TO-247
APT40M70B2VFRG
Transistor Equivalent Substitute - MOSFET Cross-Reference Search
APT40M70B2VFRG
Datasheet (PDF)
..1. Size:148K apt
apt40m70b2vfrg apt40m70lvfrg.pdf
400V 57A 0.070APT40M70B2VFR APT40M70LVFRAPT40M70B2VFRG* APT40M40LVFRG**G Denotes RoHS Compliant, Pb Free Terminal Finish.B2VFR POWER MOS V FREDFETT-MAXPower MOS V is a new generation of high voltage N-Channel enhancementTO-264mode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance
6.1. Size:62K apt
apt40m70lvr.pdf
APT40M70LVR400V 57A 0.070POWER MOS VPower MOS V is a new generation of high voltage N-Channel enhancementTO-264mode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout.. Faster Switching 100% Avalanche Tested D Lowe
6.2. Size:69K apt
apt40m70jvr.pdf
APT40M70JVR400V 53A 0.070POWER MOS VPower MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout."UL Recognized"ISOTOP Faster Switching 100% Avalanche
6.3. Size:70K apt
apt40m70jvfr.pdf
APT40M70JVFR400V 53A 0.070 POWER MOS V FREDFETPower MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS V"UL Recognized"also achieves faster switching speeds through optimized gate layout.ISOTOP Faster
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