APT5014B2VRG
MOSFET. Datasheet pdf. Equivalent
Type Designator: APT5014B2VRG
Type of Transistor: MOSFET
Type of Control Channel: N
-Channel
Pdⓘ
- Maximum Power Dissipation: 450
W
|Vds|ⓘ - Maximum Drain-Source Voltage: 500
V
|Vgs|ⓘ - Maximum Gate-Source Voltage: 30
V
|Vgs(th)|ⓘ - Maximum Gate-Threshold Voltage: 4
V
|Id|ⓘ - Maximum Drain Current: 37
A
Tjⓘ - Maximum Junction Temperature: 150
°C
Qgⓘ - Total Gate Charge: 234
nC
trⓘ - Rise Time: 15
nS
Cossⓘ -
Output Capacitance: 737
pF
Rdsⓘ - Maximum Drain-Source On-State Resistance: 0.14
Ohm
Package:
TO-247
APT5014B2VRG
Transistor Equivalent Substitute - MOSFET Cross-Reference Search
APT5014B2VRG
Datasheet (PDF)
..1. Size:55K apt
apt5014b2vrg.pdf
APT5014B2VR500V 37A 0.140POWER MOS VT-MAXPower MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout.D Faster Switching 100% Avalanche Tested Lo
3.1. Size:62K apt
apt5014b2vr.pdf
APT5014B2VR500V 37A 0.140POWER MOS VT-MAXPower MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout.D Faster Switching 100% Avalanche Tested Lo
4.1. Size:114K apt
apt5014b2vfrg apt5014lvfrg.pdf
APT5014B2VFRAPT5014LVFR500V 37A 0.140B2VFR POWER MOS V FREDFETT-MAXTO-264Power MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout.
5.1. Size:33K apt
apt5014b2lc.pdf
APT5014B2LCAPT5014LLC500V 37A 0.140WB2LCTMPOWER MOS VIT-MAXPower MOS VITM is a new generation of low gate charge, high voltageTO-264N-Channel enhancement mode power MOSFETs. Lower gate charge isachieved by optimizing the manufacturing process to minimize Ciss and Crss.Lower gate charge coupled with Power MOS VITM optimized gate layout,LLCdelivers exceptionally fast
Datasheet: WPB4002
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