ST1005SRG - Даташиты. Аналоги. Основные параметры

ST1005SRG P Channel Enhancement Mode MOSFET -0.8A DESCRIPTION ST1005SRG is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone an

DISCRETE SEMICONDUCTORSDATA SHEETBST100P-channel enhancement modevertical D-MOS transistorApril 1995Product specificationFile under Discrete Semiconductors, SC13bPhilips Semiconductors Product specificationP-channel enhancement mode verticalBST100D-MOS transistorDESCRIPTION QUICK REFERENCE DATAP-channel vertical D-MOS transistorDrain-source voltage -VDS max. 60 VT

ST1004SRG N Channel Enhancement Mode MOSFET 2.0A DESCRIPTION ST1004SRG is the N-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. The process is especially to improve the overall efficiency of DC/DC conventional switching PWM controllers. It has been optimized for low gate charge, low R and fast switchi

ST1002 N Channel Enhancement Mode MOSFET 3.0A DESCRIPTION The ST1002 is the N-Channel logic enhancement mode power field effect transistor is produce using high cell density, DMOS trench technology. This high-density process is especially tailored to minimize on-state resistance. These device are particularly suited for low voltage application such as cellular phone and notebo

JST100N30T2 30V,100A N-channel MOSFETFeatures Application 30V,100A Load Switch R =3.1m (Typ.) @ V =10V PWM ApplicationDS(ON) GS R =4.5m (Typ.) @ V =4.5VDS(ON) GS Advanced Trench Technology Provide Excellent R and Low Gate ChargeDS(ON)Package JST100N30T2 Absolute Maximum Ratings (T =25 unless otherwise specified)CSymbol Parameter