STP4953 MOSFET. Datasheet. Equivalente. Reemplazo. Hoja de especificaciones. Principales características
Número de Parte: STP4953
Tipo de FET: MOSFET
Polaridad de transistor: P
ESPECIFICACIONES MÁXIMAS
Pdⓘ - Máxima disipación de potencia: 2.7 W|Vds|ⓘ - Voltaje máximo drenador - fuente: 30 V
|Vgs|ⓘ - Voltaje máximo fuente - puerta: 20 V
|Id|ⓘ - Corriente continua de drenaje: 5.2 A
Tjⓘ - Temperatura máxima de unión: 150 °C
CARACTERÍSTICAS ELÉCTRICAS
trⓘ - Tiempo de subida: 10 nS
Cossⓘ - Capacitancia de salida: 120 pF
Rds(on)ⓘ - Resistencia estado encendido drenaje a fuente: 0.06 Ohm
Paquete / Cubierta: SOP-8
Búsqueda de reemplazo de MOSFET STP4953
STP4953 Datasheet (PDF)
stp4953.pdf
STP4953 Dual P Channel Enhancement Mode MOSFET -5.2A DESCRIPTION STP4953 is the dual P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as LCD backli
stp4953a.pdf
STP4953A -30V Dual P-Channel Fast Switching MOSFETsDESCRIPTIONFEATUREThe STP4953A is the Dual P-Channel logic -30V/-5.3A, RDS(ON) =46m(typ.)@VGS =-10V enhancement mode power field effect transistor is -30V/-3.6A, RDS(ON) =75m(typ.)@VGS =-4.5V produced using high cell density. advanced trench Super high density cell design for extremely low technology
stp4925.pdf
STP4925 Dual P Channel Enhancement Mode MOSFET -7.2A DESCRIPTION STP4925 is the dual P-Channel logic enhancement mode power field effect transistor are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application, notebook computer power
stp4931.pdf
STP4931STP4931STP4931STP4931Dual P Channel Enhancement Mode MOSFET-8.5ADESCRIPTIONDESCRIPTIONDESCRIPTIONDESCRIPTIONSTP4931 is the dual P-Channel logic enhancement mode power field effect transistorsare produced using high cell density, DMOS trench technology. This high densityprocess is especially tailored to minimize on-state resistance. These devices areparticularly
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