ST2341S23RG MOSFET. Datasheet. Equivalente. Reemplazo. Hoja de especificaciones. Principales características
Número de Parte: ST2341S23RG
Código: 41YA
Tipo de FET: MOSFET
Polaridad de transistor: P
ESPECIFICACIONES MÁXIMAS
Máxima disipación de potencia (Pd): 1.25 W
Voltaje máximo drenador - fuente |Vds|: 20 V
Voltaje máximo fuente - puerta |Vgs|: 12 V
Corriente continua de drenaje |Id|: 5.3 A
Temperatura máxima de unión (Tj): 150 °C
CARACTERÍSTICAS ELÉCTRICAS
Tensión umbral entre puerta y fuente |Vgs(th)|: 0.9 V
Carga de la puerta (Qg): 8 nC
Tiempo de subida (tr): 35 nS
Conductancia de drenaje-sustrato (Cd): 160 pF
Resistencia entre drenaje y fuente RDS(on): 0.04 Ohm
Paquete / Cubierta: SOT-23
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ST2341S23RG Datasheet (PDF)
st2341s23rg.pdf
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ST2341S23RG P Channel Enhancement Mode MOSFET -5.3A DESCRIPTION ST2341S23RG is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular pho
st2341s23r.pdf
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ST2341S23Rwww.VBsemi.twP-Channel 30 V (D-S) MOSFETFEATURESPRODUCT SUMMARY TrenchFET Power MOSFET 100 % Rg TestedVDS (V) RDS(on) () Typ.ID (A)a Qg (Typ.)0.046 at VGS = - 10 V - 5.60.049 at VGS = - 6 V - 5 11.4 nC- 30APPLICATIONS0.054 at VGS = - 4.5 V -4.5 For Mobile Computing- Load Switch- Notebook Adaptor SwitchSTO-236- DC/DC Converter(SOT-
st2341srg.pdf
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ST2341SRG P Channel Enhancement Mode MOSFET -3.2A DESCRIPTION ST2341SRG is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology.This high density process is especially tailored to minimize on-state resistance.These devices are particularly suited for low voltage application such as cellular phone and
st2341a.pdf
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ST2341A P Channel Enhancement Mode MOSFET -6.0A DESCRIPTION ST2341A is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and n
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