HUF76439S3S MOSFET. Datasheet pdf. Equivalent
Type Designator: HUF76439S3S
Type of Transistor: MOSFET
Type of Control Channel: N -Channel
Maximum Power Dissipation (Pd): 180 W
Maximum Drain-Source Voltage |Vds|: 60 V
Maximum Gate-Source Voltage |Vgs|: 16 V
Maximum Gate-Threshold Voltage |Vgs(th)|: 3 V
Maximum Drain Current |Id|: 71 A
Maximum Junction Temperature (Tj): 175 °C
Maximum Drain-Source On-State Resistance (Rds): 0.014 Ohm
Package: TO263AB
HUF76439S3S Transistor Equivalent Substitute - MOSFET Cross-Reference Search
HUF76439S3S Datasheet (PDF)
1.1. huf76439s3s.pdf 
Size:210K _fairchild_semi
HUF76439P3, HUF76439S3S Data Sheet December 2001 71A, 60V, 0.014 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB • Ultra Low On-Resistance - rDS(ON) = 0.012?, VGS = 10V SOURCE DRAIN - rDS(ON) = 0.014?, VGS = 5V DRAIN (FLANGE) GATE • Simulation Models - Temperature Compensated PSPICE® and SABER™ GATE Electrical Models SOURCE
3.1. huf76432p3-s3s.pdf Size:221K _fairchild_semi
HUF76432P3, HUF76432S3S Data Sheet December 2001 55A, 60V, 0.019 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging JEDEC TO-220AB JEDEC TO-263AB Features • Ultra Low On-Resistance SOURCE DRAIN DRAIN (FLANGE) - rDS(ON) = 0.017Ω, VGS = 10V GATE - rDS(ON) = 0.019Ω, VGS = 5V GATE • Simulation Models - Temperature Compensated PSPICE® and SABER™ SOURCE Electr
4.1. huf76443p3-s3s.pdf Size:217K _fairchild_semi
HUF76443P3, HUF76443S3S Data Sheet December 2001 75A, 60V, 0.0095 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB • Ultra Low On-Resistance SOURCE DRAIN - rDS(ON) = 0.008Ω, VGS = 10V DRAIN (FLANGE) GATE - rDS(ON) = 0.0095Ω, VGS = 5V • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™ SOURCE E
4.2. huf76407dk f085.pdf Size:542K _fairchild_semi
HUFA76407DK8T_F085 Data Sheet October 2010 3.5A, 60V, 0.105 Ohm, Dual N-Channel, Logic Level UltraFET® Power MOSFET Features Packaging JEDEC MS-012AA • Ultra Low On-Resistance - rDS(ON) = 0.090Ω, VGS = 10V BRANDING DASH - rDS(ON) = 0.105Ω, VGS = 5V • Simulation Models - Temperature Compensated PSPICE® and SABER™ 5 Electrical Models - SPICE and SABER Thermal Impedance
4.3. huf76407p3.pdf Size:214K _fairchild_semi
HUF76407P3 Data Sheet December 2001 12A, 60V, 0.107 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging JEDEC TO-220AB Features • Ultra Low On-Resistance SOURCE DRAIN - rDS(ON) = 0.092Ω, VGS = 10V GATE - rDS(ON) = 0.107Ω, VGS = 5V • Simulation Models - Temperature Compensated PSPICE® and SABER™ Electrical Models DRAIN - Spice and SABER Thermal Impedance Mo
4.4. huf76429d f085.pdf Size:346K _fairchild_semi
 HUFA76429D3ST_F085 Data Sheet September 2010 20A, 60V, 0.027 Ohm, N-Channel, Logic Level UltraFET® Power MOSFETs Packaging Features • Ultra Low On-Resistance JEDEC TO-252AA - rDS(ON) = 0.023Ω, VGS = 10V - rDS(ON) = 0.027Ω, VGS = 5V DRAIN (FLANGE) • Simulation Models - Temperature Compensated PSPICE® and SABER™ Electriecal Models GATE - Spice and SABER Thermal Im
4.5. huf76413d3-s.pdf Size:204K _fairchild_semi
HUF76413D3, HUF76413D3S Data Sheet December 2001 20A, 60V, 0.056 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging JEDEC TO-251AA JEDEC TO-252AA Features • Ultra Low On-Resistance DRAIN DRAIN SOURCE - rDS(ON) = 0.049Ω, VGS = 10V (FLANGE) (FLANGE) DRAIN GATE - rDS(ON) = 0.056Ω, VGS = 5V • Simulation Models GATE - Temperature Compensated PSPICE® and SABERâ„
4.6. huf76429d3-s.pdf Size:288K _fairchild_semi
HUF76429D3, HUF76429D3S Data Sheet February 2005 20A, 60V, 0.027 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging JEDEC TO-251AA JEDEC TO-252AA Features • Ultra Low On-Resistance DRAIN - rDS(ON) = 0.023?, VGS = 10V SOURCE (FLANGE) DRAIN - rDS(ON) = 0.027?, VGS = 5V GATE • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™ SOURCE Electrical Models D
4.7. huf76407dk8.pdf Size:266K _fairchild_semi
HUF76407DK8 Data Sheet December 2001 3.5A, 60V, 0.105 Ohm, Dual N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC MS-012AA • Ultra Low On-Resistance BRANDING DASH - rDS(ON) = 0.090Ω, VGS = 10V - rDS(ON) = 0.105Ω, VGS = 5V • Simulation Models 5 - Temperature Compensated PSPICE® and SABER™ Electrical Models 1 2 - SPICE and SABER Thermal Impedanc
4.8. huf76407d3 huf76407d3s.pdf Size:234K _fairchild_semi
HUF76407D3, HUF76407D3S Data Sheet December 2001 11A, 60V, 0.107 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging JEDEC TO-251AA JEDEC TO-252AA Features DRAIN DRAIN SOURCE • Ultra Low On-Resistance (FLANGE) (FLANGE) DRAIN GATE - rDS(ON) = 0.092?, VGS = 10V - rDS(ON) = 0.107?, VGS = 5V GATE • Simulation Models SOURCE - Temperature Compensated PSPICE® and SABER™ HUF
4.9. huf76445p3-s3s.pdf Size:214K _fairchild_semi
HUF76445P3, HUF76445S3S Data Sheet December 2001 75A, 60V, 0.0075 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB • Ultra Low On-Resistance SOURCE DRAIN - rDS(ON) = 0.0065Ω, VGS = 10V DRAIN (FLANGE) GATE - rDS(ON) = 0.0075Ω, VGS = 5V • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™ SOURCE
4.10. huf76413dk f085.pdf Size:617K _fairchild_semi
October 2010 HUFA76413DK8T_F085 N-Channel Logic Level UltraFET® Power MOSFET 60V, 4.8A, 56mΩ General Description These N-Channel power MOSFETs are manufactured us- Applications ing the innovative UltraFET® process. This advanced pro- • Motor and Load Control cess technology achieves the lowest possible on- resistance per silicon area, resulting in outstanding perfor- • Powertr
4.11. huf76423p3.pdf Size:241K _fairchild_semi
HUF76423P3, HUF76423S3S Data Sheet December 2001 33A, 60V, 0.035 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging JEDEC TO-220AB JEDEC TO-263AB Features DRAIN • Ultra Low On-Resistance SOURCE (FLANGE) DRAIN - rDS(ON) = 0.030?, VGS = 10V GATE - rDS(ON) = 0.035?, VGS = 5V GATE • Simulation Models - Temperature Compensated PSPICE® and SABER™ SOURCE Electrical Models
4.12. huf76419s f085.pdf Size:321K _fairchild_semi
April 2013 HUF76419S3ST_F085 N-Channel Power Trench® MOSFET 60V, 29A, 35mΩ D D Features Typ rDS(on) = 26.7mΩ at VGS = 10V, ID = 29A Typ Qg(tot) = 23.7nC at VGS = 10V, ID = 29A G UIS Capability RoHS Compliant G S Qualified to AEC Q101 TO-263AB S MOSFET Maximum Ratings TJ = 25°C unless otherwise noted Symbol Parameter Ratings Units VDSS Drain to Source Voltage 60 V
4.13. huf76419p3-s3s.pdf Size:220K _fairchild_semi
HUF76419P3, HUF76419S3S Data Sheet December 2001 27A, 60V, 0.040 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB • Ultra Low On-Resistance SOURCE DRAIN - rDS(ON) = 0.035Ω, VGS = 10V DRAIN (FLANGE) GATE - rDS(ON) = 0.040Ω, VGS = 5V • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™ SOURCE Elect
4.14. huf76429s3s.pdf Size:207K _fairchild_semi
HUF76429P3, HUF76429S3S Data Sheet December 2001 44A, 60V, 0.025 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-220AB JEDEC TO-263AB • Ultra Low On-Resistance DRAIN SOURCE - rDS(ON) = 0.022?, VGS = 10V DRAIN (FLANGE) GATE - rDS(ON) = 0.025?, VGS = 5V • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™ SOURCE Electrical Models D
4.15. huf76419d3s.pdf Size:197K _fairchild_semi
HUF76419D3, HUF76419D3S Data Sheet December 2001 20A, 60V, 0.043 Ohm, N-Channel, Logic Level UltraFET® Power MOSFET Packaging Features JEDEC TO-251AA JEDEC TO-252AA • Ultra Low On-Resistance - rDS(ON) = 0.037?, VGS = 10V DRAIN DRAIN - rDS(ON) = 0.043?, VGS = 5V SOURCE (FLANGE) (FLANGE) DRAIN GATE • Simulation Models - Temperature Compensated PSPICE® and SABER™ GATE Electrical
4.16. huf76423d3s.pdf Size:199K _fairchild_semi
HUF76423D3, HUF76423D3S Data Sheet December 2001 20A, 60V, 0.037 Ohm, N-Channel, Logic Level UltraFET® Power MOSFETFairchild Packaging Features JEDEC TO-251AA JEDEC TO-252AA • Ultra Low On-Resistance - rDS(ON) = 0.032?, VGS = 10V DRAIN DRAIN - rDS(ON) = 0.037?, VGS = 5V SOURCE (FLANGE) (FLANGE) DRAIN GATE • Simulation Models - Temperature Compensated PSPICE® and SABER™ GATE Ele
4.17. huf76409d3-s.pdf Size:211K _fairchild_semi
HUF76409D3, HUF76409D3S Data Sheet December 2001 17A, 60V, 0.071 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging JEDEC TO-251AA JEDEC TO-252AA Features • Ultra Low On-Resistance - rDS(ON) = 0.063Ω, VGS = 10V DRAIN DRAIN SOURCE (FLANGE) (FLANGE) - rDS(ON) = 0.071Ω, VGS = 5V DRAIN GATE • Simulation Models GATE - Temperature Compensated PSPICE® and SABER™
4.18. huf76409p3.pdf Size:111K _intersil
HUF76409P3 Data Sheet November 1999 File Number 4666.1 17A, 60V, 0.070 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging Features JEDEC TO-220AB • Ultra Low On-Resistance - rDS(ON) = 0.062Ω, VGS = 10V SOURCE - rDS(ON) = 0.070Ω, VGS = 5V DRAIN GATE • Simulation Models - Temperature Compensated PSPICE® and SABER© Electrical Models - Spice and SABER© Thermal Im
4.19. huf76413p3.pdf Size:104K _intersil
HUF76413P3 Data Sheet November 1999 File Number 4723.1 22A, 60V, 0.056 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging Features JEDEC TO-220AB • Ultra Low On-Resistance - rDS(ON) = 0.049Ω, VGS = 10V SOURCE - rDS(ON) = 0.056Ω, VGS = 5V DRAIN GATE • Simulation Models - Temperature Compensated PSPICE® and SABER© Electrical Models - Spice and SABER© Thermal Im
Datasheet: HUF76429D3S , HUF76429P3 , HUF76429S3S , HUF76432P3 , HUF76432S3S , HUF76437P3 , HUF76437S3S , HUF76439P3 , STP75NF75 , HUF76443P3 , HUF76443S3S , HUF76445P3 , HUF76445S3S , HUF76609D3 , HUF76609D3S , HUF76619D3 , HUF76619D3S .
