APT5024SFLL
MOSFET. Datasheet pdf. Equivalent
Type Designator: APT5024SFLL
Type of Transistor: MOFETS
Type of Control Channel: N
-Channel
Pdⓘ
- Maximum Power Dissipation: 265
W
|Vds|ⓘ - Maximum Drain-Source Voltage: 500
V
|Vgs|ⓘ - Maximum Gate-Source Voltage: 30
V
|Vgs(th)|ⓘ - Maximum Gate-Threshold Voltage: 5
V
|Id|ⓘ - Maximum Drain Current: 22
A
Tjⓘ - Maximum Junction Temperature: 150
°C
Qgⓘ - Total Gate Charge: 43
nC
trⓘ - Rise Time: 6
nS
Cossⓘ -
Output Capacitance: 417
pF
Rdsⓘ - Maximum Drain-Source On-State Resistance: 0.24
Ohm
Package:
D3PAK
APT5024SFLL
Transistor Equivalent Substitute - MOSFET Cross-Reference Search
APT5024SFLL
Datasheet (PDF)
..1. Size:216K microsemi
apt5024sfll apt5024sfllg.pdf
APT5024BFLL APT5024SFLL 500V 22A 0.240BFLLR POWER MOS 7 FREDFET (B)Power MOS 7 is a new generation of low loss, high voltage, N-ChannelD3PAKenhancement mode power MOSFETS. Both conduction and switch-(S)ing losses are addressed with Power MOS 7 by significantly lowering CG ERDS(ON) and Qg. Power MOS 7 combines lower conduction and switching losses along wi
6.1. Size:170K apt
apt5024bll apt5024sll.pdf
APT5024BLLAPT5024SLL500V 22A 0.240RBLL POWER MOS 7 MOSFETD3PAKPower MOS 7 is a new generation of low loss, high voltage, N-ChannelTO-247enhancement mode power MOSFETS. Both conduction and switchinglosses are addressed with Power MOS 7 by significantly lowering RDS(ON)and Qg. Power MOS 7 combines lower conduction and switching lossesSLLalong
6.2. Size:32K apt
apt5024svr.pdf
APT5024SVR500V 22A 0.240POWER MOS VPower MOS V is a new generation of high voltage N-Channel enhancementD3PAKmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS Valso achieves faster switching speeds through optimized gate layout. Faster Switching 100% Avalanche TestedD Lower Leak
6.3. Size:113K apt
apt5024svfrg.pdf
APT5024BVFRAPT5024SVFR500V 22A 0.240BVFRFREDFETPOWER MOS VD3PAKTO-247Power MOS V is a new generation of high voltage N-Channel enhancementmode power MOSFETs. This new technology minimizes the JFET effect,increases packing density and reduces the on-resistance. Power MOS VSVFRalso achieves faster switching speeds through optimized gate layout.
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