STP4925 MOSFET - описание производителя. Даташиты. Основные параметры и характеристики. Поиск аналога. Справочник
Наименование прибора: STP4925
Тип транзистора: MOSFET
Полярность: P
Максимальная рассеиваемая мощность (Pd): 2.8 W
Предельно допустимое напряжение сток-исток |Uds|: 30 V
Предельно допустимое напряжение затвор-исток |Ugs|: 20 V
Пороговое напряжение включения |Ugs(th)|: 3 V
Максимально допустимый постоянный ток стока |Id|: 7.2 A
Максимальная температура канала (Tj): 150 °C
Общий заряд затвора (Qg): 16 nC
Время нарастания (tr): 17 ns
Выходная емкость (Cd): 350 pf
Сопротивление сток-исток открытого транзистора (Rds): 0.03 Ohm
Тип корпуса: SOP-8
STP4925 Datasheet (PDF)
stp4925.pdf
STP4925 Dual P Channel Enhancement Mode MOSFET -7.2A DESCRIPTION STP4925 is the dual P-Channel logic enhancement mode power field effect transistor are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application, notebook computer power
stp4953a.pdf
STP4953A -30V Dual P-Channel Fast Switching MOSFETsDESCRIPTIONFEATUREThe STP4953A is the Dual P-Channel logic -30V/-5.3A, RDS(ON) =46m(typ.)@VGS =-10V enhancement mode power field effect transistor is -30V/-3.6A, RDS(ON) =75m(typ.)@VGS =-4.5V produced using high cell density. advanced trench Super high density cell design for extremely low technology
stp4931.pdf
STP4931STP4931STP4931STP4931Dual P Channel Enhancement Mode MOSFET-8.5ADESCRIPTIONDESCRIPTIONDESCRIPTIONDESCRIPTIONSTP4931 is the dual P-Channel logic enhancement mode power field effect transistorsare produced using high cell density, DMOS trench technology. This high densityprocess is especially tailored to minimize on-state resistance. These devices areparticularly
stp4953.pdf
STP4953 Dual P Channel Enhancement Mode MOSFET -5.2A DESCRIPTION STP4953 is the dual P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as LCD backli
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