October 1997 FDC6320C Dual N & P Channel , Digital FET General Description FeaturesThese dual N & P Channel logic level enhancement mode fieldN-Ch 25 V, 0.22 A, RDS(ON) = 5 @ VGS= 2.7 V.effec transistors are produced using Fairchild's proprietary,high cell density, DMOS technology. This very high density P-Ch 25 V, -0.12 A, RDS(ON) = 13 @ VGS= -2.7 V.process is especial

March 1999 FDC6323LIntegrated Load Switch General Description FeaturesVDROP=0.2V @ VIN=5V, IL=1A, VON/OFF= 1.5V to 8VThese Integrated Load Switches are produced usingVDROP=0.3V @ VIN=3.3V, IL=1A, VON/OFF= 1.5V to 8V.Fairchild's proprietary, high cell density, DMOStechnology. This very high density process isHigh density cell design for extremely low on-resistance.especially

April 1999 FDC6321C Dual N & P Channel , Digital FET General Description FeaturesThese dual N & P Channel logic level enhancement modeN-Ch 25 V, 0.68 A, RDS(ON) = 0.45 @ VGS= 4.5 Vfield effect transistors are produced using Fairchild'sproprietary, high cell density, DMOS technology. This very P-Ch -25 V, -0.46 A, RDS(ON) = 1.1 @ VGS= -4.5 V.high density process is especi

November 1998 FDC6329LIntegrated Load Switch General Description FeaturesThis device is particularly suited for compact powerVDROP=0.2V @ VIN=5V, IL=2.8A. R(ON) = 0.07 VDROP=0.2Vmanagement in portable electronic equipment where@ VIN=2.5V, IL=1.9A. R(ON) = 0.105.2.5V to 8V input and 2.5A output current capability areneeded. This load switch integrates a small N-Channel

July 2000FDC6327CDual N & P-Channel 2.5V Specified PowerTrenchTM MOSFETFeaturesGeneral DescriptionThese N & P-Channel 2.5V specified MOSFETs are N-Channel 2.7A, 20V. RDS(on) = 0.08 @ VGS = 4.5Vproduced using Fairchild Semiconductor's advancedRDS(on) = 0.12 @ VGS = 2.5VPowerTrench process that has been especially tailoredto minimize on-state resistance and yet mainta

March 1999 FDC6324LIntegrated Load Switch General Description FeaturesThese Integrated Load Switches are produced using Fairchild's VDROP=0.2V @ VIN=12V, IL=1A, VON/OFF=1.5 to 8V proprietary, high cell density, DMOS technology. This very highVDROP=0.3V @ VIN=5V, IL=1A, VON/OFF=1.5 to 8V.density process is especially tailored to minimize on-stateHigh density cell design for extr

FDC6321CDual N & P Channel , Digital FET FeaturesN-Ch 25 V, 0.68 A, RDS(ON) = 0.45 @ VGS= 4.5 VGeneral DescriptionP-Ch -25 V, -0.46 A, RDS(ON) = 1.1 @ VGS= -4.5 V.These dual N & P Channel logic level enhancement mode Very low level gate drive requirements allowing directfield effect transistors are produced using ON operation in 3 V circuits. VGS(th)

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FDC6321Cwww.VBsemi.twN- and P-Channel 2 V (D-S) MOSFET0 FEATURESPRODUCT SUMMARY Halogen-free According to IEC 61249-2-21VDS (V) RDS(on) ()ID (A)Definition0.024 at VGS = 10 V 5.5 TrenchFET Power MOSFETN-Channel 200.036 at VGS = 4.5 V 4.2 100 % Rg Tested0.069 at VGS = - 10 V - 3.4 Compliant to RoHS Directive 2002/95/ECP-Channel - 200.083 at V

FDC6327Cwww.VBsemi.twN- and P-Channel 2 V (D-S) MOSFET0 FEATURESPRODUCT SUMMARY Halogen-free According to IEC 61249-2-21VDS (V) RDS(on) ()ID (A)Definition0.024 at VGS = 10 V 5.5 TrenchFET Power MOSFETN-Channel 200.036 at VGS = 4.5 V 4.2 100 % Rg Tested0.069 at VGS = - 10 V - 3.4 Compliant to RoHS Directive 2002/95/ECP-Channel - 200.083 at V