FDG6321C datasheet, аналоги, основные параметры

Наименование производителя: FDG6321C  📄📄 

Тип транзистора: MOSFET

Полярность: NP

Предельные значения

Pd ⓘ - Максимальная рассеиваемая мощность: 0.3 W

|Vds|ⓘ - Максимально допустимое напряжение сток-исток: 25 V

|Vgs|ⓘ - Максимально допустимое напряжение затвор-исток: 8 V

|Id| ⓘ - Максимально допустимый постоянный ток стока: 0.5 A

Tj ⓘ - Максимальная температура канала: 150 °C

Электрические характеристики

RDSonⓘ - Сопротивление сток-исток открытого транзистора: 0.45 Ohm

Тип корпуса: SC70

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Аналог (замена) для FDG6321C

- подборⓘ MOSFET транзистора по параметрам

 

FDG6321C даташит

 ..1. Size:72K  fairchild semi
 fdg6321c.pdf pdf_icon

FDG6321C

November 1998 FDG6321C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode field N-Ch 0.50 A, 25 V, RDS(ON) = 0.45 @ VGS= 4.5V. effect transistors are produced using Fairchild's proprietary, RDS(ON) = 0.60 @ VGS= 2.7 V. high cell density, DMOS technology. This very high density process is especially tailored to mi

 ..2. Size:291K  onsemi
 fdg6321c.pdf pdf_icon

FDG6321C

Digital FET, Dual N & P Channel FDG6321C General Description These dual N & P-Channel logic level enhancement mode field www.onsemi.com effect transistors are produced using ON Semiconductor s proprietary, high cell density, DMOS technology. This very high density process is S2 especially tailored to minimize on-state resistance. This device has G2 D1 been designed especially on l

 8.1. Size:669K  fairchild semi
 fdg6322c.pdf pdf_icon

FDG6321C

June 2008 FDG6322C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 @ VGS= 4.5 V, field effect transistors are produced using Fairchild's RDS(ON) = 5.0 @ VGS= 2.7 V. proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimiz

 8.2. Size:73K  fairchild semi
 fdg6320c.pdf pdf_icon

FDG6321C

November 1998 FDG6320C Dual N & P Channel Digital FET General Description Features These dual N & P-Channel logic level enhancement mode N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 @ VGS= 4.5 V, field effect transistors are produced using Fairchild's RDS(ON) = 5.0 @ VGS= 2.7 V. proprietary, high cell density, DMOS technology. This very high density process is especially tailored to mi

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