FDG6322C MOSFET - описание производителя. Даташиты. Основные параметры и характеристики. Поиск аналога. Справочник
Наименование прибора: FDG6322C
Тип транзистора: MOSFET
Полярность: NP
Pdⓘ - Максимальная рассеиваемая мощность: 0.3 W
|Vds|ⓘ - Предельно допустимое напряжение сток-исток: 25 V
|Vgs|ⓘ - Предельно допустимое напряжение затвор-исток: 8 V
|Vgs(th)|ⓘ - Пороговое напряжение включения: 1.5 V
|Id|ⓘ - Максимально допустимый постоянный ток стока: 0.22 A
Tjⓘ - Максимальная температура канала: 150 °C
Qgⓘ - Общий заряд затвора: 0.29 nC
Rdsⓘ - Сопротивление сток-исток открытого транзистора: 4 Ohm
Тип корпуса: SC70
FDG6322C Datasheet (PDF)
fdg6322c.pdf
June 2008 FDG6322C Dual N & P Channel Digital FET General Description FeaturesThese dual N & P-Channel logic level enhancement modeN-Ch 0.22 A, 25 V, RDS(ON) = 4.0 @ VGS= 4.5 V,field effect transistors are produced using Fairchild'sRDS(ON) = 5.0 @ VGS= 2.7 V.proprietary, high cell density, DMOS technology. This veryhigh density process is especially tailored to minimiz
fdg6322c.pdf
FDG6322C Features Dual N & P Channel Digital FETN-Ch 0.22 A, 25 V, RDS(ON) = 4.0 @ VGS= 4.5 V,RDS(ON) = 5.0 @ VGS= 2.7 V. General DescriptionP-Ch -0.41 A,-25V, RDS(ON) = 1.1 @ VGS= -4.5V,These dual N & P-Channel logic level enhancement mode RDS(ON) = 1.5 @ VGS= -2.7V.field effect transistors are produced using ON Semiconductor's proprietary, high cell densit
fdg6321c.pdf
November 1998 FDG6321C Dual N & P Channel Digital FET General Description FeaturesThese dual N & P-Channel logic level enhancement mode fieldN-Ch 0.50 A, 25 V, RDS(ON) = 0.45 @ VGS= 4.5V.effect transistors are produced using Fairchild's proprietary,RDS(ON) = 0.60 @ VGS= 2.7 V.high cell density, DMOS technology. This very high densityprocess is especially tailored to mi
fdg6320c.pdf
November 1998 FDG6320C Dual N & P Channel Digital FET General Description FeaturesThese dual N & P-Channel logic level enhancement modeN-Ch 0.22 A, 25 V, RDS(ON) = 4.0 @ VGS= 4.5 V,field effect transistors are produced using Fairchild'sRDS(ON) = 5.0 @ VGS= 2.7 V.proprietary, high cell density, DMOS technology. This veryhigh density process is especially tailored to mi
fdg6321c.pdf
Digital FET, Dual N & PChannelFDG6321CGeneral DescriptionThese dual N & P-Channel logic level enhancement mode fieldwww.onsemi.comeffect transistors are produced using ON Semiconductors proprietary,high cell density, DMOS technology. This very high density process isS2especially tailored to minimize on-state resistance. This device hasG2D1been designed especially on l
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Список транзисторов
Обновления
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